參數(shù)資料
型號： QL5064-33APB456I
英文描述： BUS CONTROLLER
中文描述： 總線控制器
文件頁數(shù)： 19/37頁
文件大?。?/td> 806K
代理商： QL5064-33APB456I
QL5064 QuickPCI Data Sheet Rev D
19
QL5064 QuickPCI Data Sheet
Interrupt Control
interrupt_i
O
Active High and level sensitive. When active and not masked, asserts a
PCI interrupt.
interrupt_o
I
Active High. Indicates an interrupt is pending for the FPGA to service.
Master Arbitration Control
fpga_loc_sel[1:0]
O
FPGA arbitration select. If the FPGA has control of the master-modeling
arbitration, these bits determine which DMA channel should initiate a DMA
transfer after the next arbitration cycle. Has relationship to pci_clk.
00 => Receive channel 1 has access to the bus
01 => Receive channel 0 has access to the bus
10 => Transmit channel 1 has access to the bus
11 => Transmit channel 0 has access to the bus
fpga_bus_req[3:0]
I
Active High. Master request status. Indicates that the respective master
has need to access the PCI bus. Has relationship to pci_clk.
fpga_bus_req[0] = receive channel 1
fpga_bus_req[1] = receive channel 0
fpga_bus_req[2] = transmit channel 1
fpga_bus_req[3] = transmit channel 0
Table 1: PCI Back-End Interface Signals (Continued)
Symbol
I/O
Description
(Sheet 4 of 4)
相關(guān)PDF資料
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