參數(shù)資料
型號(hào)： QL901M-6PS680C
廠商： Electronic Theatre Controls, Inc.
英文描述： Electrical Spring Connector; Contact Termination:Twist On; Wire Size (AWG):14-10; Body Material:Flame retardant nylon; Contact Material:Spring Steel; Pack Quantity:100; Series:512; Size:2-#18 up to 5-#12; Voltage Rating:600V RoHS Compliant: Yes
中文描述： QuickMIPS ESP家庭
文件頁(yè)數(shù)： 19/37頁(yè)
文件大?。?/td> 432K
代理商： QL901M-6PS680C
QL901M QuickMIPS Data Sheet Rev B
19
Figure 19: Ethernet MAC Transmit Interface Waveforms
Table 16: PCI AC Timing
Parameter
a
a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n.
b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n.
c. All output drivers must be 3-stated when PCI_RST_n is active.
66 MHz
33 MHz
Units
Min
Max
Min
Max
Tcyc
PCI_CLK Cycle Time
15
30
ns
Thigh
PCI_CLK High Time
6
11
ns
Tlow
PCI_CLK Low Time
6
11
ns
–
PCI_CLK Slew Rate
1.5
4
1
4
V/ns
Tval
PCI_CLK to Signal Valid Delay
2
6
2
11
ns
Tval (ptp)
PCI_CLK to Signal Valid Delay
point-to-point signals
b
2
6
2
12
ns
Ton
Float to Active Delay
2
2
ns
Toff
Active to Float Delay
14
28
ns
Tsu
Input Setup Time to PCI_CLK
bused signals
3
7
ns
Tsu (ptp)
Input Setup Time to PCI_CLK
point-to-point
5
10, 12
ns
Th
Input Hold Time from PCI_CLK
0
0
ns
Trst
Reset Active Time after power stable
1
1
ms
μ
s
Trst-clk
Reset Active Time after PCI_CLK stable
100
100
Trst-off
c
Reset Active to output float delay
40
40
ns
Trhfa
PCI_RST_n high to first configuration access
2
2
clocks
Trhff
PCI_RST_n high to first PCI_FRAME_n assertion
5
5
clocks
Table 17: Ethernet MAC Transmit Interface AC Timing
Parameter
Min
Max
Units
t
en_c2q
Time from the rising clock edge of TXCLK to
the change in TXEN
8.0
ns
t
data_v
Time from the rising clock edge of TXCLK to all
data signals having valid stable values
9.0
ns
t
data_h
Time in which the output data is still valid after
the rising clock edge of TXCLK
0.0
ns
TXCLK(in)
TXEN(out)
TXD[3:0](out)
t
data_h
t
data_v
t
en_c2q
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參數(shù)描述
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