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參數(shù)資料
| 型號： | QL901M-6PS680C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Electrical Spring Connector; Contact Termination:Twist On; Wire Size (AWG):14-10; Body Material:Flame retardant nylon; Contact Material:Spring Steel; Pack Quantity:100; Series:512; Size:2-#18 up to 5-#12; Voltage Rating:600V RoHS Compliant: Yes |
| 中文描述： | QuickMIPS ESP家庭 |
| 文件頁數(shù)： | 28/37頁 |
| 文件大?。?/td> | 432K |
| 代理商： | QL901M-6PS680C |
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PCI_GNT_n
I
PCI Grant. A low assertion of PCI_GNT_n indicates to the agent that access to the bus has been
granted. PCI_GNT_n is ignored while PCI_RST_n is asserted.
PCI_IDSEL
I
PCI Initialization Device Select. PCI_IDSEL is used as a chip select during configuration read and write
transactions (PCI_C_BE_n[3:0] = 1010 or 1011).
PCI_INTA_n
O
PCI Interrupt Acknowledge. PCI_INTA_n is a level-sensitive interrupt driven by the QuickMIPS chip.
PCI_INTA_n is asserted and deasserted asynchronously to the PCI_CLK. This interrupt remains
asserted until the interrupt is cleared.
Because the PCI interrupt controller is not built into the QuickMIPS ESP core, this pin is output only.
However, such an interrupt controller can be built into the fabric.
PCI_IRDY_n
I/O
PCI Initiator Ready. PCI_IRDY_n is used in conjunction with PCI_TRDY_n. The bus master (initiator)
asserts PCI_IRDY_n to indicate when there is valid data on PCI_AD[31:0] during a write, or that it is
ready to accept data on PCI_AD[31:0] during a read.
A data phase is completed when both PCI_IRDY_n and PCI_TRDY_n are asserted. During a write, a
low assertion of PCI_IRDY_n indicates that valid data is present on PCI_AD[31:0]. During a read, a low
assertion of PCI_IRDY_n indicates the master is prepared to accept data. Wait cycles are inserted until
both PCI_IRDY_n and PCI_TRDY_n are asserted together.
PCI_LOCK_n
I
PCI Lock. A low assertion on PCI_LOCK_n indicates an atomic operation to a bridge that might take
multiple transactions to complete. When PCI_LOCK_n is asserted, non-exclusive transactions can
proceed to a bridge that is not currently locked. Control of PCI_LOCK_n is obtained under its own
protocol in conjunction with PCI_GNT_n. It is possible for different agents to use PCI while a single
master retains ownership of PCI_LOCK_n. Locked transactions can be initiated only by host bridges,
PCI-to-PCI bridges, and expansion bus bridges.
PCI_PAR
I/O
PCI Parity. Parity is driven high or low to create even parity across PCI_AD[31:0] and
PCI_C_BE_n[3:0]. The master drives PCI_PAR for address and write data phases; the target drives
PCI_PAR for read data phases.
PCI_PERR_n
I/O
PCI Parity Error. PCI_PERR_n indicates the occurrence of a data parity error during all PCI
transactions except a Special Cycle. The QuickMIPS chip drives PCI_PERR_n low two clocks following
the data when a data parity error is detected. The minimum duration of the deassertion of PCI_PERR_n
is one clock for each data phase that a data parity error is detected. (If sequential data phases each
have a data parity error, the PCI_PERR_n signal is asserted for more than a single clock.)
PCI_PERR_n is driven high for one clock before being 3-stated as with all sustained 3-state signals.
PCI_REQ_n
O
PCI Request. Assertion of PCI_REQ_n indicates to the arbiter that this agent desires use of the bus.
PCI_REQ_n is 3-stated while PCI_RST_n is asserted.
PCI_RST_n
I
PCI Reset. Asserting PCI_RST_n low resets the internal state of the QuickMIPS PCI block. When
PCI_RST_n is asserted, all PCI output signals are asynchronously 3-stated. PCI_REQ_n and
PCI_GNT_n must both be 3-stated (they cannot be driven low or high during reset).
The assertion/deassertion of PCI_RST_n can be asynchronous to PCI_CLK.
PCI_SERR_n
O
PCI System Error. The QuickMIPS chip asserts PCI_SERR_n to indicate an address parity error, a data
parity error on the Special Cycle command, or any other system error where the result is catastrophic.
PCI_SERR_n is open drain and is actively driven for a single PCI clock. The assertion of PCI_SERR_n
is synchronous to the clock and meets the setup and hold times of all bused signals. However, the
restoring of PCI_SERR_n to the deasserted state is accomplished by a weak pull-up (same value as
used for s/t/s), which is provided by the central resource not by the signaling agent. This pull-up can
take two to three clock periods to fully restore PCI_SERR_n.
PCI_STOP_n
I/O
PCI Stop. PCI_STOP_n is asserted low to indicate the current target is requesting the master to stop
the current transaction.
Table 27: Pin Descriptions (Continued)
Pin
I/O
Function
(Sheet 2 of 6)
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