參數(shù)資料
型號： QL901M-6PS680C
廠商： Electronic Theatre Controls, Inc.
英文描述： Electrical Spring Connector; Contact Termination:Twist On; Wire Size (AWG):14-10; Body Material:Flame retardant nylon; Contact Material:Spring Steel; Pack Quantity:100; Series:512; Size:2-#18 up to 5-#12; Voltage Rating:600V RoHS Compliant: Yes
中文描述： QuickMIPS ESP家庭
文件頁數(shù)： 29/37頁
文件大?。?/td> 432K
代理商： QL901M-6PS680C
QL901M QuickMIPS Data Sheet Rev B
29
PCI_TRDY_n
I/O
PCI Target Ready. PCI_TRDY_n is used in conjunction with PCI_IRDY_n. The current bus slave
(target) asserts PCI_TRDY_n to indicate when there is valid data on PCI_AD[31:0] during a read, or
that it is ready to accept data on PCI_AD[31:0] during a write.
A data phase is completed when both PCI_TRDY_n and PCI_IRDY_n are asserted. During a read, a
low assertion of PCI_TRDY_n indicates that valid data is present on PCI_AD[31:0]. During a write, a
low assertion indicates the target is prepared to accept data. Wait cycles are inserted until both
PCI_IRDY_n and PCI_TRDY_n are asserted together.
PCI_CLK
I
PCI Clock. All PCI signals (except PCI_RST_n and PCI_INTA_n) are sampled on the rising edge of
PCI_CLK. PCI_CLK operates at speeds up to either 33 MHz or 66 MHz.
Ethernet MAC Signals
M1_COL/M2_COL
I
Ethernet Collision Detected. The external Ethernet PHY Controller chip asserts COL high upon
detection of a collision on the medium. COL remains asserted while the collision condition persists.
The transitions on the COL signal are not synchronous to either the TXCLK or the RXCLK.
The QuickMIPS MAC core ignores the COL signal when operating in the full-duplex mode.
M1_CRS/M2_CRS
I
Ethernet Carrier Sense. The external Ethernet PHY Controller chip asserts CRS high when either
transmit or receive medium is non-idle. The PHY deasserts CRS low when both the transmit and
receive medium are idle. The PHY must ensure that CRS remains asserted throughout the duration of
a collision condition.
The transitions on the CRS signal are not synchronous to either the TXCLK or the RXCLK.
M1_MDC/M2_MDC
O
Ethernet Management Data Clock. MDC is sourced by the MAC110 core to the Ethernet PHY
Controller as the timing reference for transfer of information on the MDIO signals. MDC is an aperiodic
signal that has no maximum high or low times. The minimum high and low times for MDC are 160 ns
each, and the minimum period for MDC is 400 ns, regardless of the nominal period of TXCLK and
RXCLK.
M1_MDIO/M2_MDIO
I/O
Ethernet Management Data In/Out. When used as an input, MDIO is the data input signal from the
Ethernet PHY Controller. The PHY drives the Read Data synchronously with respect to the MDC clock
during the read cycles.
When used as an output, MDIO is the data output signal from the MAC110 core that drives the control
information during the Read/Write cycles to the External PHY Controller. The MAC110 core drives the
MDIO signal synchronously with respect to the MDC.
M1_RXCLK/M2_RXCLK
I
Ethernet Receive Clock. RXCLK is a continuous clock that provides the timing reference for the transfer
of the RXDV and RXD[3:0] signals from the Ethernet PHY Controller to the MAC110 core. The Ethernet
PHY Controller chip sources RXCLK. RXCLK has a frequency equal to 25% of the data rate of the
received signal on the Ethernet cable.
M1_RXD[3:0]/M2_RXD[3:0]
I
Ethernet Receive Data. RXD[3:0] transition synchronously with respect to RXCLK. The Ethernet PHY
Controller chip drives RXD[3:0]. For each RXCLK period in which RXDV is asserted, RXD[3:0] transfer
four bits of recovered data from the PHY to the MAC110 core. RXD0 is the least-significant bit. While
RXDV is deasserted low, RXD[3:0] has no effect on the MAC110 core.
M1_RXDV/M2_RXDV
I
Ethernet Receive Data Valid. The Ethernet PHY Controller asserts RXDV high to indicate to the
MAC110 core that it is presenting the recovered and decoded data bits on RXD[3:0] and that the data
on RXD[3:0] is synchronous to RXCLK. RXDV transitions synchronously with respect to RXCLK. RXDV
remains asserted continuously from the first recovered nibble of the frame through the final recovered
nibble, and is deasserted low prior to the first RXCLK that follows the final nibble.
M1_RXER/M2_RXER
I
Ethernet Receive Error. The Ethernet PHY Controller chip asserts RXER high for one or more RXCLK
periods to indicate to the MAC110 core that an error (a coding error or any error that the PHY is capable
of detecting that is otherwise undetectable by the MAC) was detected somewhere in the frame
presently being transferred from the PHY to the MAC110 core. RXER transitions synchronously with
respect to RXCLK. While RXDV is deasserted low, RXER has no effect on the MAC110 core.
Table 27: Pin Descriptions (Continued)
Pin
I/O
Function
(Sheet 3 of 6)
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