參數(shù)資料
型號(hào)： R80C52XXX-12SHXXX
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁(yè)數(shù)： 74/101頁(yè)
文件大?。?/td> 3398K
代理商： R80C52XXX-12SHXXX
97
8168C-MCU Wireless-02/10
AT86RF212
Table 7-4. O-QPSK Data Rate during PSDU
O-QPSK Data Rate [kbit/s]
Register Bits
Value
SUB_MODE = 0
SUB_MODE = 1
0
100
250
1
200
500
2
400
1000
OQPSK_DATA_RATE
3
Reserved
In Table 7-5 all PHY modes supported by the AT86RF212 are summarized with the
relevant setting for each bit of register TRX_CTRL_2. The “-“ (minus) character means
that the bit entry is not relevant for the particular PHY mode.
Table 7-5. Register 0x0C (TRX_CTRL_2) Bit Alignment
Bits of Register 0x0C
PHY Mode
7 6 5 4 3 2 1 0
Compliance
BPSK-20
-
0
IEEE 802.15.4-2003/2006:
channel page 0, channel 0
BPSK-40
-
0
1
0
IEEE 802.15.4-2003/2006:
channel page 0, channel 1 to 10
OQPSK-SIN-RC-100
-
0
1
0
IEEE 802.15.4-2006:
channel page 2, channel 0
OQPSK-SIN-RC-200
-
0
1
0
1
Proprietary
OQPSK-SIN-RC-400-SCR-ON
-
1
0
1
0
1
0
Proprietary, scrambler on
OQPSK-SIN-RC-400-SCR-OFF
-
0
1
0
1
0
Proprietary, scrambler off
OQPSK-SIN-250
-
0
1
0
IEEE 802.15.4-2006:
channel page 2, channel 1 to 10
OQPSK-SIN-500
-
0
1
0
1
Proprietary
OQPSK-SIN-1000-SCR-ON
-
1
0
1
0
Proprietary, scrambler on
OQPSK-SIN-1000-SCR-OFF
-
0
1
0
Proprietary, scrambler off
OQPSK-RC-250
-
1
0
IEEE 802.15.4c-2009 (China):
channel page 5, channel 0 to 3
OQPSK-RC-500
-
1
0
1
Proprietary
OQPSK-RC-1000-SCR-ON
-
1
0
Proprietary, scrambler on
OQPSK-RC-1000-SCR-OFF
-
0
1
0
Proprietary, scrambler off
7.2 Receiver (RX)
7.2.1 Overview
The AT86RF212 transceiver is split into an analog radio front-end and a digital domain,
see Figure 1-1. Referring to the receiver part of the analog domain, the differential RF
signal is amplified by a low noise amplifier (LNA) and split into quadrature signals by a
poly-phase filter (PPF). Two mixer circuits convert the quadrature signal down to an
intermediate frequency. Channel selectivity is achieved by an integrated band-pass
filter (BPF). The subsequent analog-to-digital converter (ADC) samples the receive
signal and additionally generates a digital RSSI signal, see section 6.4. The ADC output
is then further processed by the digital baseband receiver (RX BBP), which is part of
the digital domain.
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