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參數(shù)資料
| 型號： | R80C52XXX-12SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 98/101頁 |
| 文件大小： | 3398K |
| 代理商： | R80C52XXX-12SHXXX |
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AT86RF212
7.7.3 External Reference Frequency Setup
When using an external reference frequency, the signal must be connected to
pin 26 (XTAL1) as indicated in Figure 7-16. The oscillation peak-to-peak amplitude shall
be between 100 mV and 500 mV; the optimum range is between 400 mV and 500 mV.
It is possible, among other things, to use sine and square wave signals. Note that the
quality of the external reference (i.e. phase noise) determines the system performance.
Pin 25 (XTAL2) should not be wired. For power saving reasons, it is recommended to
set register bits XTAL_MODE (register 0x12, XOSC_CTRL) to the external oscillator
mode.
Figure 7-16. Setup for Using an External Frequency Reference
7.7.4 Master Clock Signal Output (CLKM)
The generated reference clock signal can be fed into a microcontroller using
pin 17 (CLKM). The internal 16 MHz raw clock can be divided by an internal prescaler.
Thus, clock frequencies of 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 250 kHz, or the
current SHR symbol rate frequency can be supplied by pin CLKM.
The CLKM frequency, update scheme, and pin driver strength is configurable using
register 0x03 (TRX_CTRL_0). There are two possibilities how a CLKM frequency
change gets effective. If CLKM_SHA_SEL = 0 and/or CLKM_CTRL = 0, changing the
register bits CLKM_CTRL immediately affects the CLKM clock rate. Otherwise
(CLKM_SHA_SEL = 1 and CLKM_CTRL > 0 before changing the register bits
CLKM_CTRL), the new clock rate is supplied when leaving the SLEEP state the next
time.
To reduce power consumption and spurious emissions, it is recommended to turn off
the CLKM clock when not in use or to reduce its driver strength to a minimum, refer to
section 2.2.2.
CLKM reset behavior
During reset procedure (see section 5.1.4.5), register bits CLKM_CTRL are shadowed.
Although the clock setting of CLKM remains after reset, a read access to register bits
CLKM_CTRL delivers the reset value 1. For that reason, it is recommended to write the
previous configuration (before reset) to register bits CLKM_CTRL (after reset) to align
the radio transceiver behavior and register configuration. Otherwise, the CLKM clock
rate is set back to the reset value (1 MHz) after the next SLEEP cycle.
For example, if the CLKM clock rate is configured to 16 MHz, the CLKM clock rate
remains at 16 MHz after a reset, however, the register bits CLKM_CTRL are set back to
1. Since CLKM_SHA_SEL reset value is 1, the CLKM clock rate changes to 1 MHz
after the next SLEEP cycle if the CLKM_CTRL setting is not updated.
119
8168C-MCU Wireless-02/10
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