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參數(shù)資料
| 型號： | RH56D-PCI |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | Host Controlled V.90/K56flex Modem device |
| 中文描述： | 主機(jī)控制V.90/K56flex調(diào)制解調(diào)器設(shè)備 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大?。?/td> | 357K |
| 代理商： | RH56D-PCI |
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RH56D-PCI Modem Designer’s Guide
1213
Conexant
4-5
Conexant Proprietary Information
4.1.8 Telephone and Local Handset Interface
1. Place common mode chokes in series with Tip and Ring for each connector.
2. Decouple the telephone line cables at the telephone line jacks. Typically, use a combination of series inductors, common
mode chokes, and shunt capacitors. Methods to decouple telephone lines are similar to decoupling power lines,
however, telephone line decoupling may be more difficult and deserves additional attention. A commonly used design aid
is to place footprints for these components and populate as necessary during performance/EMI testing and certification.
3. Place high voltage filter capacitors (.001 μF @1KV) from Tip and Ring to digital ground.
4.1.9 Optional Configurations
Because fixed requirements of a design may alter EMI performance, guidelines that work in one case may deliver little or no
performance enhancement in another. Initial board design should, therefore, include flexibility to allow evaluation of optional
configurations. These optional configurations may include:
1. Chokes in Tip and Ring lines replaced with jumper wires as a cost reduction if the design has sufficient EMI margin.
2. Various grounding areas connected by tie points (these tie points can be short jumper wires, solder bridges between
close traces, etc.).
3. Develop two designs in parallel; one based on a 2-layer board and the other based on a 4-layer board. During the
evaluation phase, better performance of one design over another may result in quicker time to market.
4.1.10 MDP Specific
1. Locate the MDP device and all supporting analog circuitry, including the data access arrangement, on the same area of
the PCB.
2. Locate the analog components close to and on the side of board containing the TXA1, TXA2, RXA, TELIN, TELOUT,
MIC_V, and SPKOUT signals.
3. Avoid placing noisy components and traces near the TXA1, TXA2, RXA, TELIN, TELOUT, MIC_V, and SPKOUT lines.
4. Route MDP modem interconnect signals by the shortest possible route avoiding all analog components.
5. Provide an RC network on the AVAA supply in the immediate proximity of the AVAA pin to filter out high frequency noise
above 115 kHz. A tantalum capacitor is recommended (especially in a 2-layer board design) for improved noise immunity
with a current limiting series resistor or inductor to the VCC supply which meets the RC filter frequency requirements.
6. Provide a 0.1 μF ceramic decoupling capacitor to ground between the high frequency filter and the VAA pin.
7. Provide a 0.1 μF ceramic decoupling capacitor to ground between the VCC supply and the AVDD pin.
4.2 CUSTOM DESIGN GUIDELINES FOR 2-LAYER PCI MODEM BOARD
Purpose of this section is to provide additional design guidelines customized for PCI boards utilizing only two layers. For a
complete summary of PCB design guidelines, refer to the Section 4.1.
4.2.1 General Guidelines
1. Tie separate ground planes together at only one point.
2. Fill bare board areas (top and bottom) with ground or Vcc (use 50-50 ratio or favor ground).
3. Provide 15 to 40 mil spacing between analog and digital ground traces.
4. Provide 25 mil minimum width for power and ground traces.
5. Provide 15 mil minimum width for crystal traces.
6. Avoid inconsistencies in routing; EMI radiation will occur every time a trace changes it’s impedance.
7. Prevent turns greater than 45 degrees.
8. Prevent different thickness on a trace.
9. Apply ground fill under crystals.
10. Follow the examples illustrated in Section 4.3.
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