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參數(shù)資料
| 型號： | RH56D-PCI |
| 廠商： | Conexant Systems, Inc. |
| 英文描述： | Host Controlled V.90/K56flex Modem device |
| 中文描述： | 主機控制V.90/K56flex調(diào)制解調(diào)器設備 |
| 文件頁數(shù)： | 50/60頁 |
| 文件大?。?/td> | 357K |
| 代理商： | RH56D-PCI |
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RH56D-PCI Modem Designer’s Guide
5-2
Conexant
1213
Conexant Proprietary Information
5.1.3 0x04 - Command Register
The Command Register bits are described in Table 5-2.
7DEOH &RPPDQG 5HJLVWHU
Bit
Description
0
Controls a device’s response to I/O Space accesses. A value of 0 disables the device response. A value
of 1 allows the device to respond to I/O Space accesses. The bit state is 0 after PCIRST# is deasserted.
Controls a device’s response to Memory Space accesses. A value of 0 disables the device response. A
value of 1 allows the device to respond to Memory Space accesses. The bit state is 0 after PCIRST# is
deasserted.
Controls a device’s ability to act as a master on the PCI Bus. A value of 0 disables the device from
generating PCI accesses. A value of 1 allows the device to behave as a bus master. The bit state is 0
after PCIRST# is deasserted.
Not Implemented.
This bit controls the device’s response to parity errors. When the bit is set, the device must take its
normal action when a parity error is detected. When the bit is 0, the device must ignore any parity errors
that it detects and continue normal operation. The bit state is 0 after PCIRST# is deasserted.
This bit is used to control whether or not a device does address/data stepping. This bit is read only from
the PCI interface. The bit state is loaded from the serial EEPROM after PCIRST# is deasserted.
This bit is an enable bit for the SERR# driver. A value of 0 disables the SERR# driver. A value of 1
enables the SERR# driver. The bit state is 0 after PCIRST# is deasserted.
This bit controls whether or not a master can do fast back-to-back transactions to different devices. A
value of 1 means the master is allowed to generate fast back-to-back transactions to different agents as
described in Section 3.4.2 of the PCI 2.1 specification. A value of 0 means fast back-to-back transactions
are only allowed to the same agent. The bit state is 0 after PCIRST# is deasserted.
Reserved
1
2
3-5
6
7
8
9
10-15
5.1.4 0x06 - Status Register
The Status Register bits are described in Table 5-3.
Status register bits may be cleared by writing a ‘1’ in the bit position corresponding to the bit position to be cleared. It is not
possible to set a status register bit by writing from the PCI Bus. Writing a ‘0’ has no effect in any bit position.
7DEOH 6WDWXV 5HJLVWHU
Bit
Description
0-3
Reserved
This bit is set to indicate the presence of the Capabilities Pointer pointing to Power Management registers
(0x40, 0x44).
Not Implemented.
This bit is only implemented by bus masters. It is set when three conditions are met: 1) the bus agent
asserted PERR# itself or observed PERR# asserted; 2) the agent setting the bit acted as the bus master
for the operation in which the error occurred; and 3) the Parity Error Response bit (Command Register) is
set.
These bits encode the timing of DEVSEL#. These are encoded as 00 for fast, 01 for medium, and 10 for
slow (11 is reserved.) These bits are read-only and must indicate the slowest time that a device asserts
DEVSEL# for any bus command except Configuration Read and Configuration Write.
Not Implemented.
This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All
master devices must implement this bit.
This bit must be set by a master device whenever its transaction (except for Special Cycle) is terminated
with Master-Abort. All master devices must implement this bit.
This bit must be set whenever the device asserts SERR#. Devices which will never assert SERR# do not
need to implement this bit.
This bit must be set by the device whenever it detects a parity error, even if parity error handling is
disabled (as controlled by bit 6 in the Command register).
4
5-7
8
9-10
11
12
13
14
15
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