參數(shù)資料
型號(hào)： RH56D-PCI
廠商： Conexant Systems, Inc.
英文描述： Host Controlled V.90/K56flex Modem device
中文描述： 主機(jī)控制V.90/K56flex調(diào)制解調(diào)器設(shè)備
文件頁(yè)數(shù)： 51/60頁(yè)
文件大?。?/td> 357K
代理商： RH56D-PCI
RH56D-PCI Modem Designer’s Guide
1213
Conexant
5-3
Conexant Proprietary Information
5.1.5 0x08 - Revision ID Field
Value hardcoded in the device.
5.1.6 0x09 - Class Code Field
Loaded from the serial EEPROM after after PCIRST# is deasserted.
5.1.7 0x0D - Latency Timer Register
The Latency Timer register specifies, in units of PCI Bus clocks, the value of the Latency Timer for this PCI Bus master. This
register has 5 read/write bits (MSBs) plus 3 bits of hardwired zero (LSBs). The Latency Timer Register is loaded into the PCI
Latency counter each time FRAME# is asserted to determine how long the master is allowed to retain control of the PCI Bus.
This register is loaded by system software. The default value for Latency Timer is 00.
5.1.8 0x0E - Header Type Field
Hardwired to 00.
5.1.9 0x28 - CIS Pointer Register
This register points to the CIS memory located in the BIF’s memory space.
5.1.10 0x2C - Subsystem Vendor ID Register
Subsystem Vendor ID register is supported. Loaded from the serial EEPROM after PCIRST# is deasserted.
5.1.11 0x2E- Subsystem ID Register
Subsystem ID register is supported. Loaded from the serial EEPROM after PCIRST# is deasserted.
5.1.12 0x34 - Cap Ptr
Capabilities Pointer (CAP_PTR) at offset 0x34 containing hardcoded value 0x40.
5.1.13 0x3C - Interrupt Line Register
The Interrupt Line register is a read/write 8-bit register. POST software will write the value of this register as it initializes and
configures the system. The value in this register indicates which of the system interrupt controllers the device’s interrupt pin is
connected to.
5.1.14 0x3D - Interrupt Pin Register
The Interrupt Pin register tells which interrupt pin the device uses. The value of this register will be 0x01, indicating that
INTA# will be used.
5.1.15 0x3E - Min Grant Register
The Min Grant register is used to specify the devices desired settings for Latency Timer values. The value specifies a period
of time in units of 0.25 microsecond. Min Grant is used for specifying the desired burst period assuming a 33 MHz clock. This
register is loaded from the serial EEPROM after PCIRST# is deasserted.
5.1.16 0x3F - Max Latency Register
The Max Latency register is used to specify the devices desired settings for Latency Timer values. The value specifies a
period of time in units of 0.25 microsecond. Min Latency specifies how often the device needs to gain access to the PCI Bus.
This register is loaded from the serial EEPROM after PCIRST# is deasserted.
5.1.17 0x40 - Capability Identifier
The Capability Identifier is set to 01h to indicate that the data structure currently being pointed to is the PCI Power
Management data structure.
5.1.18 0x41 - Next Item Pointer
The Next Item Pointer register describes the location of the next item in the function’s capability list. The value given is an
offset into the function’s PCI Configuration Space. The value of 00h indicates there are no additional items in the capabilities
list.
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