參數(shù)資料
型號： RH80532NC025256
元件分類： 微處理器
英文描述： Microprocessor
中文描述： 微處理器
文件頁數(shù)： 80/93頁
文件大?。?/td> 2353K
代理商： RH80532NC025256
Mobile Intel
Pentium
4 Processor-M Datasheet
80
Datasheet
250686-002
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
DSTBN[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
Input/
Output
Data strobe used to latch in D[63:0]#.
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating-point error and will be asserted when the processor
detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/
PBE# is similar to the ERROR# signal on the INTEL 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-point error
reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that
the processor has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to the Normal state.
When FERR#/PBE# is asserted, indicating a break event, it will remain asserted
until STPCLK# is deasserted. For additional information on the pending break
event functionality, including the identification of support of the feature and enable/
disable information, refer to volume 3 of the
Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID Instruction
application
note.
GHI#
Input
The GHI# signal controls the selection of the operating mode bus ratio and voltage
in the Mobile Intel Pentium 4 Processor-M. On the Mobile Intel Pentium 4
Processor-M featuring Enhanced Intel SpeedStep technology, this signal is latched
on entry to Sleep state and is observed during the Deep Sleep state. GHI#
determines which of two performance states is selected for operation. This signal is
ignored when the processor is not in the Deep Sleep state. This signal should be
driven with an Open-drain driver. For connection and termination guidelines refer to
the
Mobile Intel
Pentium
4 Processor-M and Intel
845MP/845MZ Chipset
Platform Design Guide.
GTLREF
Input
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3 V
. GTLREF is used by the AGTL+ receivers to determine if a
signal is a logical 0 or logical 1. Refer to the
Mobile Intel
Pentium
4 Processor-M
and Intel
845MP/845MZ Chipset Platform Design Guide
for more information.
Table 36. Signal Description (Page 4 of 8)
Name
Type
Description
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBP0#
D[31:16]#, DBI1#
DSTBP1#
D[47:32]#, DBI2#
DSTBP2#
D[63:48]#, DBI3#
DSTBP3#
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相關代理商/技術參數(shù)
參數(shù)描述
RH80532NC029256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
RH80532NC033256 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
RH80532NC049256 制造商:Rochester Electronics LLC 功能描述:- Bulk
RH80532NC049256S L8SB 制造商:Intel 功能描述:INTEL CELERON PROCESSOR AVAILABLE AT 1.60 GHZ, 1.8 GHZ, 2.00 GHZ, 2.2 GHZ
RH80532NC049256S-L8SB 制造商:Intel 功能描述:INTEL CELERON PROCESSOR AVAILABLE AT 1.60 GHZ, 1.8 GHZ, 2.00 GHZ, 2.2 GHZ
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