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參數(shù)資料
| 型號： | RK80532PC041512 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 16/86頁 |
| 文件大小： | 882K |
| 代理商： | RK80532PC041512 |
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16
Datasheet
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.3
Power and Ground Pins
The operating voltage for the Intel Pentium
III
processor with 512KB L2 Cache is the same for
the core and the L2 cache. V
CCCORE
is defined as the power pins that supply voltage to the
processor’s core and cache. The voltage regulator module (VRM) or voltage regulator is
controlled by the five voltage identification (VID) signals driven by the processor.
signals specify the voltage required by the processor core. Refer to
Section 2.6
for further details
on the VID voltage settings.
The VID
The Intel Pentium
III
processor with 512KB L2 cache has 74 V
CCCORE
, 7 V
REF
, 20 V
TT
,
V
CCCMOS1.5
, V
CCCMOS1.8,
V
CCCMOS2.0
and 74 V
SS
inputs. The V
REF
inputs are used as the AGTL
reference voltage for the processor. The V
TT
inputs (1.25V) are used to provide an AGTL
termination voltage to the processor. V
CCCMOS1.5
and V
CCCMOS1.8
and V
CCCMOS2.0
are not
voltage input pins to the processor but rather voltage sources for the pullup resistors which are
connected to CMOS (non-AGTL) input/output signals driven to/from the processor. The V
SS
inputs are ground pins for the processor core and L2 cache.
On the platform, all V
CCCORE
pins must be connected to a voltage island (an island is a portion of
a power plane that has been divided, or an entire plane) to minimize any voltage drop that may
occur due to trace impedance. It is also highly recommended for the platform to provide either a
voltage island or a wide trace for the V
TT
pins. Similarly, all Vss pins must be connected to a
system ground plane. These recommendations can be found in the platform design guide layout
section.
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL. Please refer to the Phase Lock Loop Power section in
the appropriate platform design guide for the recommended filter implementation.
Figure 4. PLL Filter Specification
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