參數(shù)資料
型號(hào)： RK80532PC041512
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 23/86頁(yè)
文件大小： 882K
代理商： RK80532PC041512
Datasheet
23
Intel
Pentium
III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.8.2
System Bus Frequency Select Signals
The System Bus Frequency Select Signals (BSEL [1:0]) are used to select the system bus
frequency for the Intel Pentium
III
processor. The BSEL signals are also used by the chipset and
system bus clock generator. The BSEL pins for the Intel Pentium
III
processor with 512KB L2
Cache are open drain signals versus opens or shorts found on the previous Intel
Pentium
III
processor in the FC-PGA package. Refer to
Table 11
for level specifications for the BSEL signals.
The BSEL signals rely on a 3.3V pull-up resistor to set the signal to a logic high level. Similar to
the VID signals described in
Section 2.6
, the VTT_PWRGD signal also informs the platform that
the BSEL signals are stable and should be sampled. During power-up, the BSEL signals will be in
an indeterminate state for a small period of time. The chipset or system bus clock generator should
not sample and/or latch the BSEL signals until the VTT_PWRGD signal is asserted. The assertion
of the VTT_PWRGD signal indicates the BSEL signals are stable and are driven to the final state
by the processor. Refer to
Figure 14
for power-up timing sequence for the VTT_PWRGD and the
BSEL signals.
Table 5
defines the possible combinations of the BSEL signals and the frequency associated with
each combination. The frequency selection is determined by the processor(s) and driven out to the
chipset and system bus clock generator. All system bus agents must operate at the same frequency
determined by the processor. The Intel Pentium
III
processor with 512KB L2 Cache operates
at 133MHz system bus frequency based on the system bus specified rating marked on the package.
Over or under-clocking the system bus frequency outside the specified rating marked on the
package is not recommended.
Figure 7. BSEL[1:0] Example for a System Design
Table 5.
Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Frequency
0
0
Reserved
0
1
Reserved
1
0
Reserved
1
1
133 MHz
P r o c e s s o r
B S E L 0
B S E L 1
C h ip s e t
C lo c k
D r iv e r
1 K
o h m
K o h m
3 .3 V
3 .3 V
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