參數(shù)資料
型號: RS5C372B
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: I2C-bus Serial Interface Real Time Clock (8pin SSOP)
中文描述: REAL TIME CLOCK, PDSO8
封裝: SSOP-8
文件頁數(shù): 18/39頁
文件大小: 474K
代理商: RS5C372B
RS5C372B
- 18 -
times per unit time) means number of transition from “H” to “L” of the signal line.
Calculation example is shown below:
Pull-up resistance (RP)=10k
, Bus capacity=50pF (both for SCL and SDA), VDD=3V
In as system with sum of input current and off state output current of each pin=0.1μA, I
2
C-bus is used for
10ms every second while the rest of 990ms is in the stand-by mode. In this mode number of transitions of
the SCL pin from “H” to “L” state is 100 while SDA 50.
Bus consumption current
0.1μA
×
990msec
990msec+10msec
+ 3V
×
10msec
×
2
10K
×
2
×
(990msec + 10msec)
+ 3V
×
50pF
×
(100 + 50)
0.099μA+3.0μA+0.0225μA
3.12μA
Generally, the second member of the above formula is larger enough than the first and the third members,
bus consumption current may be determined by the second member.
1.2. I
2
C-bus transmission system
1.2.1. Start Condition and Stop Condition
In I
2
C-bus, SDA must be kept at a certain state while SCL is at the “H” state as shown below during data
transmission.
The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to “L”
when the SCL and the SDA are “H” activates the Start Condition and access is started. Changing the SDA from
“L” to “H” when the SCL is “H” activates Stop Condition and accessing stopped. Generation of Start and Stop
Conditions are always made by the master (see the figure below).
Start Condition
SCL
SDA
tSU;DAT
tHDH;DAT or tHDL;DAT
SCL
SDA
tHD;STA
tSU;STO
Stop Condition
1.2.2. Data transmission and its acknowledge
After start condition is entered, data is transmitted by 1 byte (8 bits). Any bytes of data may be serially transmitted.
The receiver will send an acknowledge signal to the transmission side each time 8bit data is transmitted. The
acknowledge signal is sent immediately after falling to “L” of SCL8bit clock pulses of data transmission, by
releasing the SDA by the transmitter that has asserted the bus at that time and by turning the
SDA to “L” by the
receiver. When transmission of 1 byte data next to preceding 1 byte of data is received the receiver releases the
SDA pin at falling edge of the SCL 9 bit of clock pulses or when the receiver switches to the transmitter it starts data
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