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參數(shù)資料
| 型號(hào)： | RTL8100C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| 中文描述： | 單芯片快速以太網(wǎng)控制器電源管理 |
| 文件頁數(shù)： | 49/73頁 |
| 文件大?。?/td> | 652K |
| 代理商： | RTL8100C |
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RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
41
Track ID: JATR-1076-21 Rev. 1.06
6.3. PCI Configuration Space Status
Status:
The status register is a 16-bit register used to record status information for PCI bus related events.
Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set.
Table 42. PCI Configuration Space Status
Bit
15
Symbol
DPERR
Description
Detected Parity Error.
When set indicates that the RTL8100C(L) detected a parity error, even if parity error handling is
disabled in the command register PERRSP bit.
Signaled System Error.
When set indicates that the RTL8100C(L) asserted the system error pin, SERRB.
Writing a 1 clears this bit to 0.
Received Master Abort.
When set indicates that the RTL8100C(L) terminated a master transaction with master abort.
Writing a 1 clears this bit to 0.
Received Target Abort.
When set indicates that the RTL8100C(L) master transaction was terminated due to a target abort.
Writing a 1 clears this bit to 0.
Signaled Target Abort.
Set to 1 whenever the RTL8100C(L) terminates a transaction with target abort. Writing a 1 clears this
bit to 0.
Device Select Timing.
These bits encode the timing of DEVSELB. They are set to 01b (medium), indicating the
RTL8100C(L) will assert DEVSELB two clocks after FRAMEB is asserted.
Data Parity error Detected.
This bit sets when the following conditions are met:
The RTL8100C(L) asserts parity error(PERRB pin) or it senses the assertion of PERRB pin by
another device.
14
SSERR
13
RMABT
12
RTABT
11
STABT
10-9
DST1-0
8
DPD
The RTL8100C(L) operates as a bus master for the operation that caused the error.
The Command register PERRSP bit is set.
Writing a 1 clears this bit to 0.
Fast Back-To-Back Capable.
Config3<FbtBEn>=0, Read as 0. Write operation has no effect.
Config3<FbtBEn>=1, Read as 1.
User Definable Features.
Read as 0. Write operation has no effect.
The RTL8100C(L) does not support UDF.
66MHz Capable.
Read as 0. Write operation has no effect.
The RTL8100C(L) has no 66MHz capability.
New Capability.
Config3<PMEn>=0, Read as 0. Write operation has no effect.
Config3<PMEn>=1, Read as 1.
Reserved.
7
FBBC
6
UDF
5
66MHz
4
NewCap
0-3
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RTL8100C-LF | SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100CL | SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8130 | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100 | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100B | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RTL8100CL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100C-LF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8100CL-LF | 制造商:Realtek Semiconductor 功能描述:RTL8100CL Series 3.6 V Fast Ethernet Controller with Power Management LQFP-128 |
| RTL8100L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
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