參數(shù)資料
型號(hào)： RTL8100C
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
中文描述： 單芯片快速以太網(wǎng)控制器電源管理
文件頁數(shù)： 51/73頁
文件大?。?/td> 652K
代理商： RTL8100C
RTL8100C & RTL8100CL
Datasheet
Single-Chip Fast Ethernet Controller
43
Track ID: JATR-1076-21 Rev. 1.06
MEMAR: Memory Address Register
This register specifies the base memory address for memory accesses to the RTL8100C(L) operational
registers. This register must be initialized prior to accessing any of the RTL8100C(L)’s registers with
memory access.
Table 44. Base Memory Address for Memory Accesses
Description
MEM31-8 Base Memory Address.
This is set by software to the base address for the operational register map.
MEMSIZE Memory Size.
These bits return 0, which indicates that the RTL8100C(L) requires 256 bytes of Memory Space.
MEMPF
Memory Pre-Fetchable.
Read only. Set to 0 by the RTL8100C(L).
MEMLOC Memory Location Select.
Read only. Set to 0 by the RTL8100C(L).
This indicates that the base register is 32-bits wide and can be placed anywhere in the 32-bit memory
space.
MEMIN
Memory Space Indicator.
Read only. Set to 0 by the RTL8100C(L) to indicate that it is capable of being mapped into memory
space.
Bit
31-8
Symbol
7-4
3
2-1
0
SVID:
Subsystem Vendor ID
This field will be set to a value corresponding to the PCI Subsystem Vendor ID in the external EEPROM. If
there is no EEPROM, this field will default to a value of 10ECh (Realtek Semiconductor’s PCI Subsystem
Vendor ID).
SMID: Subsystem ID.
This field will be set to a value corresponding to PCI Subsystem ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 8139h.
BMAR: Bus Master Address Register
This register is disabled in the RTL8100C(L).
ILR: Interrupt Line Register
The Interrupt Line Register is an 8-bit read-only register used to indicate the routing of the interrupt. It is
written by the POST software to set an interrupt line for the RTL8100C(L).
IPR: Interrupt Pin Register (Read Only IPR = 01H)
The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8100C(L). The
RTL8100C(L) uses an INTA interrupt pin.
MNGNT: Minimum Grant Timer (Read Only)
Specifies the minimum burst period the RTL8100C(L) needs at a 33MHz clock rate, in units of 1/4
microseconds. This field will be set to a value from the external EEPROM. If there is no EEPROM, this
field will default to a value of 20h.
MXLAT: Maximum Latency Timer (Read Only)
Indicates how long the RTL8100C(L) is allowed access to the PCI bus, in units of 1/4 microseconds. This
field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a
value of 20h.
相關(guān)PDF資料
PDF描述
RTL8100C-LF SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RTL8100CL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100C-LF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8100CL-LF 制造商:Realtek Semiconductor 功能描述:RTL8100CL Series 3.6 V Fast Ethernet Controller with Power Management LQFP-128
RTL8100L 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
RTL8101 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT
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