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參數(shù)資料
| 型號： | RTL8139C |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| 中文描述： | 瑞昱3.3V的單芯片快速以太網(wǎng)控制器電源管理 |
| 文件頁數(shù)： | 21/62頁 |
| 文件大?。?/td> | 648K |
| 代理商： | RTL8139C |
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RTL8139C(L)
2002/01/10
Rev.1.4
21
6.11 CONFIG 1: Configuration Register 1
(Offset 0052h, R/W)
Bit
R/W
Symbol
7-6
R/W
LEDS1-0
5
R/W
DVRLOAD
Description
Refer to LED PIN definition. These bits’ initial value come from 93C46/93C56.
Driver Load:
Software may use this bit to make sure that the driver has been
loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,
MEMEN, and BMEN of the PCI configuration space are written, the
RTL8139C(L) will clear this bit automatically.
LWAKE active mode:
The LWACT bit and LWPTN bit in the CONFIG4
register are used to program the LWAKE pin’s output signal. According to the
combination of these two bits, there may be 4 choices of LWAKE signal, i.e.,
active high, active low, positive (high) pulse, and negative (low) pulse. The
output pulse width is about 150 ms. In CardBus applications, the LWACT and
LWPTN have no meaning.
The default value of each of these two bits is 0, i.e., the default output signal of
the LWAKE pin is an active high signal.
0
Active high*
LWPTN
1
Positive pulse
* Default value.
Memory Mapping:
The operational registers are mapped into PCI memory space.
I/O Mapping:
The operational registers are mapped into PCI I/O space.
Vital Product Data:
This is used to set to enable Vital Product Data. The VPD
data is stored in 93C46 or 93C56 from within offset 40h-7Fh.
Power Management Enable:
Write able only when 93C46CR register EEM1=EEM0=1
Let A denote the New_Cap bit (bit 4 of the Status Register) in the PCI
Configuration space offset 06H.
Let B denote the Cap_Ptr register in the PCI Configuration space offset 34H.
Let C denote the Cap_ID (power management) register in the PCI Configuration
space offset 50H.
Let D denote the power management registers in the PCI Configuration space
offset from 52H to 57H.
Let E denote the Next_Ptr (power management) register in the PCI
Configuration space offset 51H.
LWACT
LWAKE output
0
1
Active low
Negative pulse
4
R/W
LWACT
3
2
1
R
R
MEMMAP
IOMAP
VPD
R/W
0
R/W
PMEn
PMEn Description
0 A=B=C=E=0, D not valid
1 A=1, B=50h, C=01h, D valid, E=0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RTL8139L | REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8139 | REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8139A | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8139B | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8139D | REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RTL8139C_PLUS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RTL8139C_Plus Specification |
| RTL8139CL | 制造商:Realtek Semiconductor 功能描述: |
| RTL8139CL+ | 制造商:Realtek Semiconductor 功能描述: |
| RTL8139D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE-CHIP MULTI-FUNCTION 10/100Mbps ETHERNET CONTROLLER WITH POWER MANAGEMENT |
| RTL8139D(L) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RTL8139D(L) Specification |
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