MC9S12DT128 Device User Guide — V02.09
62
PH4
KWH4
---
—
—
VDDR
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
PERH/
PPSH
Disabled Port H I/O, Interrupt
PH3
KWH3
SS1
—
—
VDDR
Disabled
Port H I/O, Interrupt,
SS of SPI1
Port H I/O, Interrupt,
SCK of SPI1
Port H I/O, Interrupt,
MOSI of SPI1
Port H I/O, Interrupt,
MISO of SPI1
Port J I/O, Interrupt,
TX of CAN4, SCL of
IIC
Port J I/O, Interrupt,
RX of CAN4, SDA of
IIC
PH2
KWH2
SCK1
—
—
VDDR
Disabled
PH1
KWH1
MOSI1
—
—
VDDR
Disabled
PH0
KWH0
MISO1
—
—
VDDR
Disabled
PJ7
KWJ7
TXCAN4
SCL
TXCAN0
VDDX
PERJ/
PPSJ
Up
PJ6
KWJ6
RXCAN4
SDA
RXCAN0
VDDX
PERJ/
PPSJ
Up
PJ[1:0]
KWJ[1:0]
—
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, Interrupts
PK7
ECS
ROMCTL
—
—
VDDX
PUCR/
PUPKE
Up
Port K I/O,
Emulation Chip
Select, ROM Control
Port K I/O, Extended
Addresses
Port M I/O, BF slot
mismatch pulse, TX
of CAN4
Port M I/O, BF illegal
pulse/message
format error pulse,
RX of CAN4
Port M I/O, BF
reception ok pulse,
TX of CAN0, CAN4,
SCK of SPI0
Port M I/O, BF sync
pulse (Rx/Tx) OK
pulse o/p, RX of
CAN0, CAN4, MOSI
of SPI0
Port M I/O, TX of BF,
CAN1, CAN0, SS of
SPI0
Port M I/O, RX of BF,
CAN1, CAN0, MISO
of SPI0
Port M I/O, TX of
CAN0, RX of BDLC
Port M I/O, RX of
CAN0, RX of BDLC
PK[5:0]
XADDR[19:
14]
—
—
—
VDDX
PUCR/
PUPKE
Up
PM7
BF_PSLM
TXCAN4
—
—
VDDX
PERM/
PPSM
Disabled
PM6
BF_PERR
RXCAN4
—
—
VDDX
PERM/
PPSM
Disabled
PM5
BF_PROK
TXCAN0
TXCAN4
SCK0
VDDX
PERM/
PPSM
Disabled
PM4
BF_PSYN
RXCAN0
RXCAN4
MOSI0
VDDX
PERM/
PPSM
Disabled
PM3
TX_BF
TXCAN1
TXCAN0
SS0
VDDX
PERM/
PPSM
Disabled
PM2
RX_BF
RXCAN1
RXCAN0
MISO0
VDDX
PERM/
PPSM
Disabled
PM1
TXCAN0
TXB
—
—
VDDX
PERM/
PPSM
PERM/
PPSM
Disabled
PM0
RXCAN0
RXB
—
—
VDDX
Disabled
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Pin Name
Function 5
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Internal Pull
Resistor
Description
CTRL
Reset
State