參數(shù)資料
型號: S71GL064A08BFI0B2
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA56
封裝: 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56
文件頁數(shù): 34/134頁
文件大?。?/td> 2383K
代理商: S71GL064A08BFI0B2
February 8, 2005 S71GL064A_00_A2
Type 1 SRAM
127
Advance
Informatio n
Data Retention Characteristics
4M Version F
Notes:
1. CS1 controlled:CS1#
VCC-0.2V. CS2 controlled: CS2 ≤ 0.2V.
2. Typical values are not 100% tested.
W
rite
Write cycle time
tWC
70
-
ns
Chip select to end of write
tCW
60
-
ns
Address set-up time
tAS
0
-
ns
Address valid to end of write
tAW
60
-
ns
LB#, UB# valid to end of write
tBW
60
-
ns
Write pulse width
tWP
50
-
ns
Write recovery time
tWR
0
-
ns
Write to output high-Z
tWHZ
0
20
ns
Data to write time overlap
tDW
30
-
ns
Data hold from write time
tDH
0
-
ns
End write to output low-Z
tOW
5
-
ns
Item
Symbol
Test Condition
Min
Typ
Max Unit
VCC for data retention
VDR
CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V. BYTE# = VSS or VCC 1.5
-
3.3
V
Data retention current
IDR
VCC=3.0V, CS1# ≥ VCC-0.2V (Note 1), VIN ≥ 0V
-
1.0
10
A
Data retention set-up time
tSDR
See data retention waveform
0
-
ns
Recovery time
tRDR
tRC
-
Table 33. Read/Write Characteristics (VCC=2.7-3.3V) (Continued)
Parameter List
Symbol
Speed Bins
Units
70ns
Min
Max
相關(guān)PDF資料
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S71GL064A08BFI0B3 Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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