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參數(shù)資料
| 型號： | S71GL064A08BFI0B2 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Product (MCP) Flash Memory and RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA56 |
| 封裝： | 7 X 9 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-56 |
| 文件頁數(shù)： | 50/134頁 |
| 文件大?。?/td> | 2383K |
| 代理商： | S71GL064A08BFI0B2 |
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20
S71GL064A based MCPs
S71GL064A_00_A2 February 8, 2005
Advance
Info rmation
valid data on the device data outputs. The device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table
for timing specifications and the timing diagram. Refer to the DC Characteristics table for the
active current specification on reading array data.
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask
ROM read operation. This mode provides faster read access speed for random locations within
a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by
the higher address bits A(max)–A2. Address bits A1–A0 in word mode (A1–A-1 in byte mode)
determine the specific word within a page. This is an asynchronous operation; the micropro-
cessor supplies the specific word location.
The random or initial page access is equal to tACC or tCE and subsequent page read accesses
(as long as the locations specified by the microprocessor falls within that page) is equivalent
to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is
tACC or tCE. Fast page mode accesses are obtained by keeping the “read-page addresses” con-
stant and changing the “intra-read page” addresses.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device
and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facilitate faster programming. Once the de-
vice enters the Unlock Bypass mode, only two write cycles are required to program a word,
instead of four. The “Word Program Command Sequence” section has details on programming
data to the device using both standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Refer to the DC Characteristics table for the active current specification for the write mode.
The AC Characteristics section contains timing specification tables and timing diagrams for
write operations.
Write Buffer
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one
programming operation. This results in faster effective programming time than the standard
programming algorithms. See “Write Buffer” for more information.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of
two functions provided by the WP#/ACC or ACC pin, depending on model number. This func-
tion is primarily intended to allow faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Un-
lock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher
voltage on the pin to reduce the time required for program operations. The system would use
a two-cycle program command sequence as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC or ACC pin, depending on model number, returns the device to normal
operation. Note that the WP#/ACC or ACC pin must not be at VHH for operations other than
accelerated programming, or device damage may result. WP# has an internal pullup; when
unconnected, WP# is at VIH.
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