246
32072H–AVR32–10/2012
AT32UC3A3
17. Error Corrected Code Controller (ECCHRS)
Rev. 1.0.0.0
17.1
Features
Hardware Error Corrected Code Generation with two methods :
– Hamming code detection and correction by software (ECC-H)
– Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS)
Supports NAND Flash and SmartMedia devices with 8- or 16-bit data path for ECC-H, and with
8-bit data path for ECC-RS
Supports NAND Flash and SmartMedia with page sizes of 528, 1056, 2112, and 4224 bytes
(specified by software)
ECC_H supports :
– One bit correction per page of 512,1024,2048, or 4096 bytes
– One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096
bytes
– One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096
bytes
ECC_RS supports :
– 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and
4096 bytes with 8-bit data path
17.2
Overview
NAND Flash and SmartMedia
devices contain by default invalid blocks which have one or
more invalid bits. Over the NAND Flash and SmartMedia lifetime, additional invalid blocks may
occur which can be detected and corrected by an Error Corrected Code (ECC).
The ECC Controller is a mechanism that encodes data in a manner that makes possible the
identification and correction of certain errors in data. The ECC controller is capable of single-bit
error correction and two-bit random detection when using the Hamming code (ECC-H) and up to
four symbols (a symbol is a 8-bit data) correction whatever the number of errors in symbol (1 to
8 bits of error) when using the Reed-Solomon code (ECC-RS).
When NAND Flash/SmartMedia have more than two erroneous bits when using the Hamming
code (ECC-H) or more than four bits in error when using the Reed-Solomon code (ECC-RS), the
data cannot be corrected.