331
32072H–AVR32–10/2012
AT32UC3A3
a.
Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
b.
If the hardware handshaking interface is activated for the source or destination
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DEST_PER bits, respectively.
4.
Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the
the last Linked List Item must be set as described in Row 1 or Row 5 of
Table 19-1 on5.
Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the
last) are non-zero and point to the base address of the next Linked List Item.
6.
Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory
point to the start source/destination block address preceding that LLI fetch.
7.
Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI
entries in memory are cleared.
8.
Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
9.
Program the CTLx, CFGx registers according to Row 10 as shown in
Table 19-1 on10. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
11. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
performed.
12. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note:
The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automati-
cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).
13. Source and destination request single and burst DMA transactions to transfer the block
of data (assuming non-memory peripheral). The DMACA acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
Note:
14. The DMACA does not wait for the block interrupt to be cleared, but continues fetching
the next LLI from the memory location pointed to by current LLPx register and automat-
ically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA
transfer continues until the DMACA determines that the CTLx and LLPx registers at the
327. The DMACA then knows that the previous block transferred was the last block in