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型號：	S83C154DXXX-30D
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44
文件頁數(shù)：	627/1021頁
文件大?。?/td>	15196K
代理商：	S83C154DXXX-30D

32072H–AVR32–10/2012

AT32UC3A3

Special considerations for control endpoints

If a SETUP packet is received into a control endpoint for which a STALL is requested, the

Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are

cleared. The SETUP has to be ACKed.

This management simplifies the enumeration process management. If a command is not sup-

ported or contains an error, the user requests a STALL and can return to the main task, waiting

for the next SETUP request.

STALL handshake and retry mechanism

The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the

STALLRQ bit is set and if there is no retry required.

Management of control endpoints

A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,

but not the Received OUT Data Interrupt (RXOUTI) bit.

The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in

UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these

endpoints. When read, their value are always zero.

Control endpoints are managed using:

The RXSTPI bit which is set when a new SETUP packet is received and which shall be

cleared by firmware to acknowledge the packet and to free the bank.

The RXOUTI bit which is set when a new OUT packet is received and which shall be cleared

by firmware to acknowledge the packet and to free the bank.

The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to

accept a new IN packet and which shall be cleared by firmware to send the packet.

Control write

Figure 27-14 on page 644 shows a control write transaction. During the status stage, the control-

ler will not necessarily send a NAK on the first IN token:

If the user knows the exact number of descriptor bytes that must be read, it can then

anticipate the status stage and send a zero-length packet after the next IN token.

Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the

bytes have been sent by the host and that the transaction is now in the status stage.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S83C154-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-12	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-20	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S83C154T-25	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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