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您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25635 > S83C154DXXX-30D (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44 PDF資料下載

型號(hào)：	S83C154DXXX-30D
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44
文件頁(yè)數(shù)：	374/1021頁(yè)
文件大?。?/td>	15196K
代理商：	S83C154DXXX-30D

32072H–AVR32–10/2012

AT32UC3A3

low level is driven by an external master on the NPCS0/NSS signal.

When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR

is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable

bit in the CR register (CR.SPIEN).

By default, the mode fault detection circuitry is enabled. The user can disable mode fault detec-

tion by writing a one to the Mode Fault Detection bit in the MR register (MR.MODFDIS).

SPI Slave Mode

When operating in slave mode, the SPI processes data bits on the clock provided on the SPI

clock pin (SPCK).

The SPI waits for NSS to go active before receiving the serial clock from an external master.

When NSS falls, the clock is validated on the serializer, which processes the number of bits

defined by the Bits Per Transfer field of the Chip Select Register 0 (CSR0.BITS). These bits are

processed following a phase and a polarity defined respectively by the CSR0.NCPHA and

CSR0.CPOL bits. Note that the BITS, CPOL, and NCPHA bits of the other Chip Select Registers

have no effect when the SPI is configured in Slave Mode.

The bits are shifted out on the MISO line and sampled on the MOSI line.

When all the bits are processed, the received data is transferred in the Receive Data Register

and the SR.RDRF bit rises. If the RDR register has not been read before new data is received,

the SR.OVRES bit is set. Data is loaded in RDR even if this flag is set. The user has to read the

SR register to clear the SR.OVRES bit.

When a transfer starts, the data shifted out is the data present in the Shift Register. If no data

has been written in the TDR register, the last data received is transferred. If no data has been

received since the last reset, all bits are transmitted low, as the Shift Register resets to zero.

When a first data is written in TDR, it is transferred immediately in the Shift Register and the

SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls

and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in

TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent

updates of critical variables with single transfers.

Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to

be transmitted, i.e. no character has been written in TDR since the last load from TDR to the

Shift Register, the Shift Register is not modified and the last received character is retransmitted.

In this case the Underrun Error Status bit is set in SR (SR.UNDES).

Figure 21-9 on page 416 shows a block diagram of the SPI when operating in slave mode.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S83C154-L16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-12	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-16	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-20	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller
S83C154T-25	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:8-Bit Microcontroller

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