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參數(shù)資料
| 型號： | SAA2022GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, SOT-208A, QFP-64 |
| 文件頁數(shù)： | 25/52頁 |
| 文件大小： | 208K |
| 代理商： | SAA2022GP |
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February 1994
25
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
Notes to Fig.16b.
Note
1.
t
LE
is determined by the longest path from LTEN LOW to LTDATA. This path is via the reset of the internal bit counter.
This reset is only necessary when after the last LTEN = LOW, an exact multiple of 8-bits has not been transferred.
Otherwise t
LE
can be T
cy
= 165 ns less.
DESCRIPTION
TIMING
For the timing figures it is assumed that cycle time T
cy
of MCLK is within the limits 160 ns < T
cy
< 165 ns
The set-up time t
su
of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH
t
su
< 40 ns
The hold time t
h
of LTEN, LTCNT, LTCLK and LTDATA to MCLK HIGH
t
h
= 0 ns
The delay time t
d
of LTDATA from MCLK HIGH is within the limits
0 ns < t
d
< 30 ns
The delay time t
d
of LTEN to the 3-state control of LTDATA
0 ns < t
d
< 50 ns
LTEN LOW time before start data transfer
t
LE
> 535 ns; note 1
LTCLK LOW time
t
Lc
> 205 ns
LTCLK HIGH time
t
Hc
> 205 ns
LTCNT0/1 set-up time to LTEN HIGH
t
su1
> 205 ns
LTCNT0/1 hold time from LTEN HIGH
t
h1
> 205 ns
LTEN set-up time to LTCLK LOW
t
su2
> 0 ns
LTEN hold time from LTCLK HIGH
t
h2
> 205 ns
LTCLK set-up time to LTEN HIGH
t
su4
> 535 ns
LTCLK hold time from LTEN LOW
t
h5
> 160 ns
LTDATA hold time from LTEN LOW
t
h6
> 0 ns
LTDATA delay time from LTEN HIGH
t
d1
< 235 ns
LTDATA delay time from LTCLK HIGH
t
d2
< 400 ns
LTDATA delay time from LTEN (3-state control)
t
d4
< 50 ns
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