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參數(shù)資料
| 型號： | SAA2022GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Tape formatting and error correction for the DCC system |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, SOT-208A, QFP-64 |
| 文件頁數(shù)： | 37/52頁 |
| 文件大小： | 208K |
| 代理商： | SAA2022GP |
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February 1994
37
Philips Semiconductors
Product specification
Tape formatting and error
correction for the DCC system
SAA2022
B
LOCK OFFSETS WITH RESPECT TO TIME SEGMENT
Mode DPAP
SYSBlk = (SNUM + 3) MOD 4;
or read all 4 SYSINFO blocks when SNUM = 1.
If AUX and MAIN were recorded simultaneously then
AUXBlk = (SNUM + 1) MOD 4; else read and interpret
1 AUX block in each time segment.
Mode DRAR
SYSBlk = SNUM;
AUXBlk = (SNUM + 1) MOD 4.
Mode DPAR
SYSBlk = (SNUM + 3) MOD 4;
or read all 4 SYSINFO blocks when SNUM = 1;
AUXBlk = (SNUM + 1) MOD 4.
T
HE
S
CRATCH
P
AD
RAM
The SAA2022 provides the microcontroller with a scratch
pad RAM, which it can use for any purpose. The size of the
scratch pad depends upon the size of the DRAM used and
the locations may be written and read in 8-bit or 12-bit
units.
For a 64 k
×
4-bit DRAM, the scratch pad is arranged as
6 pages, where each page consists of
7 columns
×
64 rows. The pages are numbered 0 to 5,
columns 1 to 7 and rows 0 to 63. This gives a total of
(6
×
7
×
64) = 2688 locations.
For a 256 k
×
4-bit DRAM, the scratch pad is the same as
for the 64 k
×
4 bit DRAM, plus an additional 3 RAM
quarters, each of 6 pages where each page consists of
8 columns
×
448 rows. The pages are numbered 0 to 5,
columns 0 to 7 and rows 0 to 431. This gives then a total
of (2688 + (3
×
6
×
8
×
448)) = 67200 locations. The RAM
quarter is chosen by the YZ bits of the microcontroller
interface commands.
Use of the scratch pad RAM outside the above ranges will
upset the operation of the device.
As with SYSINFO, AUX transfers can occur at high-speed
at all times except the second half of time segment 0, that
is when the status bit SLOWTFR is HIGH. During this
period the microcontroller must poll the status bit RFBT to
determine when a transfer can occur.
There are two possible methods for addressing the scratch
pad RAM. For random access of the scratch pad the
address of each location is sent by the microcontroller to
the SAA2022 before each location transfer. Alternatively,
the address of the first location can be sent by the
microcontroller before the first location transfer. This will
automatically increment the row for all subsequent
transfers until the end of the column. The RACCNT and
BYTCNT registers are used for addressing the scratch
pad. For the 64 k
×
4-bit DRAM, and first quarter of
256 k
×
4 DRAM the mapping of the scratch pad RAM
address onto the RACCNT and BYTCNT registers is
shown in Tables 20 and 21. For the other three-quarters of
the 256 k
×
4 DRAM the mapping of the scratch pad RAM
address onto the RACCNT and BYTCNT registers is
shown in Tables 22 and 23.
Table 20
RACCNT bit.
Table 21
BYTCNT bit.
RACCNT BIT
6
5
4
3
2
1
0
P2
P1
P0
C2
C1
C0
1
BYTCNT BIT
7
6
5
4
3
2
1
0
1
0
R5
R4
R3
R2
R1
R0
Table 22
RACCNT bit.
Table 23
BYTCNT bit.
RACCNT BIT
6
5
4
3
2
1
0
P2
P1
P0
C2
C1
C0
R8
BYTCNT BIT
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
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