參數(shù)資料
型號(hào)： SAA3323H
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Drive processor for DCC systems
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, TQFP-80
文件頁(yè)數(shù)： 30/56頁(yè)
文件大?。?/td> 274K
代理商： SAA3323H
May 1994
30
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
SAA3323 test pins
TEST0
TO
TEST3
These input pins are for test only,
do not connect
.
AZCHK
This output pin indicates the occurrence of a tape channel
sync symbol on tape channels TCH0 and TCH7, the
distance between the pulses for the TCH0 and TCH7
channels gives a measure of the azimuth error between
the tape and head alignment. Figure 25 shows the typical
timing for this signal.
handbook, full pagewidth
MEA705
(8 periods MCLK)
1.3
μ
s
This is a measure of the azimuth error.
Duration of the one tape block
5.3 ms
AZCHK
Fig.25 AZCHK timing.
Nominal Inter Frame Gap (IFG) lasts 660
μ
s.
ERCOSTAT
This output pin can be connected to a symbol error rate
measurement system.
Port expansion pins
PINI
This input pin is connected directly to the PINI bit in the
status byte 1, it can be read by the microcontroller, and
may be used for any CMOS level compatible input signals.
PINO1
This output pin is connected directly to the PINO1 bit of the
TFE settings 0 register. The microcontroller can set or
reset this pin.
PINO2
TO
PINO5
Depending upon the type and the size of system RAM
used, some or all of these Port expander output pins may
be available, (please see Section “RAM connections”
“A10 and A12 to A16” on interfacing to the RAM pins).
Supply pins
V
DD1
TO
V
DD6
These are the supply pins, all of these pins must be
connected. We recommend that each power supply pin
pair (i.e. V
DD1
to V
SS1
, V
DD2
to V
SS2
, etc.) be decoupled
using a 22 nF capacitor as close as is physically possible
to the pins of the SAA3323.
V
SS1
TO
V
SS6
These are the supply ground pins, all of which must be
connected.
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