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參數(shù)資料
| 型號： | SAA3323H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, TQFP-80 |
| 文件頁數(shù)： | 38/56頁 |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323H |
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May 1994
38
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
RD1 and RD0 return delay
This is the delay before returning to normal mode after
being in ‘extended range mode’ (i.e. the number of
consecutive channel clock bit periods where the bit clock
frequency falls within the normal range before the clock
extraction returns to normal frequency mode).
Table 42
RD1 and RD0 return delay.
SYSINFO and AUX data offsets in the SAA3323
AUX data consists of 4 blocks of 36 bytes, one block being
transferred in each (n) time segment.
RD
DELAY IN BITS TO RETURN TO
NORMAL MODE
1
0
0
0
1
1
0
1
0
1
64
128
256
512
The 128 bytes in each tape frame contain SYSINFO. The
SYSINFO bytes can for convenience, be considered as
being grouped into 4 SYSINFO blocks with:
SYSBLK0
→
SI0 to SI31, SYSBLK1
→
SI31 to SI63, etc.
In modes DPAP and DRAR SYSINFO transfers may occur
in two ways:
1.
4 blocks of 36 bytes, one block being transferred to the
SAA3323 in each time segment.
2.
1 block of 128 bytes being transferred in time
segment 1.
In mode DRAR SYSINFO must be transferred as 4 blocks
of 32 bytes, one block in each segment.
Figures 31 to 34 show the offsets between the SYSINFO
and AUX and the time segment counter, for the various
modes of operation of the SAA3323.
Table 43
Block offsets with respect to time segment.
MODE
DESCRIPTION
DPAP
SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0; if AUX and
main were recorded simultaneously then AUXBLK = (SNUM + 1) MOD4; else read and interpret
1 AUX block in each time segment.
SYSBLK = SNUM; AUXBLK = (SNUM + 1) MOD4
SYSBLK = (SNUM + 3) MOD4; or read all 4 SYSINFO blocks when SNUM = logic 0
DRAR
DPAR
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