參數(shù)資料
型號: SAA3323H
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Drive processor for DCC systems
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, TQFP-80
文件頁數(shù): 48/56頁
文件大?。?/td> 274K
代理商: SAA3323H
May 1994
48
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Inputs/outputs
C
I
C
L
A11
TO
A16
input capacitance
load capacitance
10
20
pF
pF
t
d
delay time from SLEEP HIGH to
SLEEP active
propagation delay time from falling
edge of CLK24
25
ns
t
pd
55
ns
D0
TO
D3
t
d
delay time from SLEEP HIGH to
SLEEP active
set-up time to falling edge of CLK24
hold time from falling edge of CLK24
propagation delay time
from falling edge of CLK24
from rising edge of CLK24
20
ns
t
su
t
h
t
pd
5
15
ns
ns
50
50
ns
ns
early write mode
D4
TO
D7
t
d
delay time from SLEEP HIGH to
SLEEP active
set-up time to falling edge of CLK24
hold time from falling edge of CLK24
propagation delay time
from falling edge of CLK24
from rising edge of CLK24
25
ns
t
su
t
h
t
pd
5
15
ns
ns
50
50
ns
ns
early write mode
L3DATA
t
d
delay time from SLEEP HIGH to
SLEEP active
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
propagation delay time
from rising edge of MCLK
from L3MODE
25
ns
t
su
t
h
t
pd
35
0
ns
ns
50
45
ns
ns
SBCL
AND
SBWS
t
d
delay time from SLEEP HIGH to
SLEEP active
set-up time to rising edge of MCLK
hold time from rising edge of MCLK
propagation delay time
from rising edge of SBMCLK
from rising edge of MCLK
(3-state control)
25
ns
t
su
t
h
t
pd
40
0
ns
ns
60
55
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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