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參數(shù)資料
| 型號： | SAA4956TJ |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 存儲器 |
| 英文描述： | 2.9-Mbit field memory with noise reduction |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO40 |
| 封裝： | PLASTIC, SOJ-40 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 243K |
| 代理商： | SAA4956TJ |
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1998 Dec 08
14
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
7.2.5
N
OISE SHAPE
If the noise shaping is activated possible shadow picture
information in the chrominance and the luminance path,
resulting from a low K-factor value, will be eliminated.
The noise shaping function can be switched off by means
of the I
2
C-bus control. Subregister noise_shape = 0 is
applied to show the effect.
7.3
I
2
C-bus interface
The I
2
C-bus interface in the SAA4956TJ is used in a
receive mode. The standardized bus frequencies of both
100 kHz and 400 kHz can be dealt with.
As a slave receiver, the SAA4956TJ provides 8 registers
for storing commands and data. These registers are
accessed via so-called subaddresses. A subaddress can
be thought of as a pointer to an internal memory location.
It is allowed to send one data byte or more data bytes per
transmission to the SAA4956TJ. In this event, the
subaddress is automatically incremented after each data
byte, resulting in storing the sequence of data bytes at
successive register locations, starting at SUBADDRESS.
A transmission can start at any valid subaddress. Each
data byte is acknowledged with ACK (acknowledge).
There is no ‘wrap around’ of subaddresses. Commands
and data are processed as soon as they have been
completely received. Data patterns sent to the various
subaddresses are not checked for being illegal or not at
that address. Detection of a STOP condition without a
preceding acknowledge bit is regarded as a bus error.
The last operation will not then be executed. Invalid
subaddresses are not acknowledged.
The default I
2
C-bus settings can be loaded by changing
the state of the NREN pin from LOW to HIGH during
clocking of the SWCK and SCL pins. This can be realized
for example by delaying the NREN signal with an
RC-circuit for 1 second during the power-up sequence.
This is necessary to give the circuit a minimum of
20 cycles of SCL and 100 cycles of SWCK after all input
signals are stabilized.
Table 4
I
2
C-bus control; slave address, subaddress and data format
Table 5
Description of bits used in Table 4
S
SLAVE ADDRESS
0
ACK
SUBADDRESS
ACK
DATA
ACK
...
DATA
ACK
P
BIT
FUNCTION
S
SLAVE ADDRESS
0
ACK
SUBADDRESS
DATA
P
START condition
7-bit device address: 1011 111 (last bit is LSB)
data direction bit (write to device)
acknowledge
address of register to write to
data byte to be written into register
STOP condition
相關(guān)PDF資料 |
PDF描述 |
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| SAA4960 | Integrated PAL comb filter |
| SAA4963 | Integrated NTSC comb filter |
| SAA4963T | Integrated NTSC comb filter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA4960 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated PAL comb filter |
| SAA4963 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated NTSC comb filter |
| SAA4963T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated NTSC comb filter |
| SAA4970T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Economical video processing IC ECOBENDIC |
| SAA4974 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Besic without ADC |
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