參數(shù)資料
型號(hào)： SAA4956TJ
廠商： NXP SEMICONDUCTORS
元件分類： 存儲(chǔ)器
英文描述： 2.9-Mbit field memory with noise reduction
中文描述： SPECIALTY MEMORY CIRCUIT, PDSO40
封裝： PLASTIC, SOJ-40
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 243K
代理商： SAA4956TJ
1998 Dec 08
18
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
Notes
1.
Typical values are valid for T
amb
= 25
°
C, V
DD
= V
DD(O)
= V
DD(P)
= 3.3 V, all voltages referenced to GND. See Fig.1
for configuration.
The AC characteristics are in accordance with the I
2
C-bus specification for fast mode (clock frequency maximum
400 kHz). Information about the I
2
C-bus can be found in the brochure “The I
2
C-bus and how to use it”(order number
9398 393 40011).
The write cycle timing set-up and hold times are related to V
IL
of the rising edge of SWCK. They are valid for the
specified LOW and HIGH-level input voltages (V
IL
and V
IH
).
The read cycle timing set-up and hold times are related to V
IL
of the rising edge of SRCK. They are valid for the
specified LOW and HIGH-level input voltages (V
IL
and V
IH
). The load on each output is a 30 pF capacitor to ground
in parallel with a 218
resistor to 1.31 V.
Disable times specified are from the initiating edge until the output is no longer driven by the memory. Disable times
are measured by observing the output waveforms. Low values of load resistor and capacitor have to be used to
obtain a short time constant.
2.
3.
4.
5.
t
su(D)
t
h(D)
t
su(RSTW)
t
h(RSTW)
t
su(WE)
t
h(WE)
t
W(WEL)
t
su(IE)
t
h(IE)
t
W(IEL)
t
t
set-up time data inputs (D0 to D11) see Fig.4
hold time data inputs (D0 to D11)
set-up time RSTW
hold time RSTW
set-up time WE
hold time WE
WE LOW pulse width
set-up time IE
hold time IE
IE LOW pulse width
transition time (rise and fall)
5
3
5
3
5
3
8
5
3
8
3
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
see Fig.4
see Fig.4
see Fig.4
see Fig.8
see Fig.8
see Fig.8
see Fig.9
see Fig.9
see Fig.9
see Fig.4
Read cycle timing;
note 4
t
ACC
t
en(Q)
t
dis(Q)
t
h(Q)
T
cy(SRCK)
t
W(SRCKH)
t
W(SRCKL)
t
su(RSTR)
t
h(RSTR)
t
su(RE)
t
h(RE)
t
W(REL)
t
su(OE)
t
h(OE)
t
W(OEL)
t
t
access time after SRCK
output enable time after SRCK
output disable time after SRCK
output hold time after SRCK
SRCK cycle time
HIGH-level pulse width of SRCK
LOW-level pulse width of SRCK
set-up time RSTR
hold time RSTR
set-up time RE
hold time RE
LOW-level pulse width of RE
set-up time OE
hold time OE
LOW-level pulse width of OE
transition time (rise and fall)
see Fig.11
see Fig.15
note 5; see Fig.15
see Fig.11
see Fig.11
see Fig.11
see Fig.11
see Fig.11
see Fig.11
see Fig.14
see Fig.14
see Fig.14
see Fig.15
see Fig.15
see Fig.15
see Fig.11
3
26
7
7
5
3
5
3
9
5
3
9
3
21
21
12
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
(1)
MAX.
UNIT
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