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參數(shù)資料
| 型號(hào)： | SAA4956TJ |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | 2.9-Mbit field memory with noise reduction |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PDSO40 |
| 封裝： | PLASTIC, SOJ-40 |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大小： | 243K |
| 代理商： | SAA4956TJ |
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1998 Dec 08
5
Philips Semiconductors
Preliminary specification
2.9-Mbit field memory with noise reduction
SAA4956TJ
5
BLOCK DIAGRAM
Fig.1 Block diagram.
Pin 21 (V
) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance, 5.0 V
instead of 3.3 V. Pins 19 and 22 (V
DD
and V
DD(O)
) require a 3.3 V supply.
handbook, full pagewidth
MGR687
SERIAL WRITE REGISTER
20-WORD (
×
13)
mini cache write/read2 control
+
cache transfer
mini cache read control
OE
internal
DATA MUX
D-field delay
PARALLEL WRITE REGISTER
20-WORD (
×
13)
20
×
(12
+
1)
I
2
C-bus control
12
+
1
12
12
12
MEMORY ARRAY
245760-WORD (
×
12)
SAA4956TJ
MEMORY
ARBITRATION
LOGIC
WRITE ADDRESS
COUNTER
REFRESH ADDRESS
COUNTER
READ ADDRESS
COUNTER
WRITE REGISTER
DATA INPUT AND
WRITE MASK
BUFFER (
×
13)
INPUT BUFFER
(
×
3)
SERIAL WRITE/READ2 CONTROLLER
CLOCK
OSCILLATOR
IE
internal
OE
internal
D0
internal
20
×
(12
+
1)
12
27 to 38
23
OE
Q0(V0) to Q11(Y7)
RE
RSTR SRCK
24
25
26
12
22
100 nF
12
14 to 3
18
17
16
15
12
+
1
12
+
1
+
3.3 V
READ
REGISTER
READ2
REGISTER
MINI CACHE
12-WORD (
×
12)
DATA MUX
DATA OUTPUT
BUFFER (
×
12)
INPUT BUFFER
(
×
4)
DATA
MUX
NOISE
REDUCTION
12
READ2 ADDRESS
COUNTER
IE internal
D0 internal
SERIAL READ CONTROLLER
3
3
write
control
read2
control
write
acknowledge
read2
acknowledge
read
control
PARALLEL READ REGISTER
20-WORD (
×
12)
20
×
12
SERIAL READ REGISTER
20-WORD (
×
12)
20
×
12
PARALLEL READ2 REGISTER
20-WORD (
×
12)
20
×
12
SERIAL READ2 REGISTER
20-WORD (
×
12)
20
×
12
read
acknowledge
load write
block
address
load read
block
address
refresh
clock
IE
internal
IE
WE
RSTW SWCK
40
1
20
NREN
SCL
SDA
2
GND
39
OGND
VDD(O)
21
VDD(P)
19
VDD
I
2
C-BUS
INTERFACE
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