參數(shù)資料
型號(hào)： SAA4970T
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Economical video processing IC ECOBENDIC
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO56
封裝： PLASTIC, SOT-190-1, VSOP-56
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 179K
代理商： SAA4970T
1996 Oct 25
14
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
ECO-PLL
In the PLL block, 3 functions are performed with the
following sub-blocks:
Crystal oscillator
PLL core
Clock and R1 divider for multi picture.
C
RYSTAL OSCILLATOR
The crystal oscillator should drive an external 12 MHz
crystal used in the watchdog and externally by e.g. the
microcontroller.
PLL
CORE
In the PLL core, line locked clocks are made for both the
acquisition and display sides of the double scan
conversion circuits. The PLL can lock its outputs to an
externally applied Hs 16 kHz line pulse. The outputs are:
CK2, the display clock
CL1, the (basic) acquisition clock
R2, the display 32 kHz line frequent pulse
RL1, the (basic) 16 kHz line frequent pulse.
The CK2 frequency relates to the Hs frequency with a
factor determined by PLL_div:
PLL_div = 0
→
CK2 = 2
×
1024
×
Hs (nominal 32 MHz)
PLL_div = 1
→
CK2 = 2
×
864
×
Hs (nominal 27 MHz)
PLL_div = 2
→
CK2 = 2
×
768
×
Hs (nominal 24 MHz)
PLL_div = 3
→
CK2 = 2
×
648
×
Hs
(nominal 20.25 MHz).
The C
p
and C
i
settings in the PLL2 control byte correspond
to coefficients in the proportional and integrating parts of
the PLL control loop.
The actual proportional coefficient is 2
(Cp + 1)
. With C
p
ranging from 0 to 7, 2
(Cp + 1)
ranges from
1
2
to
1
256
.
The actual integrating coefficient is 2
(Ci + 2)
. With C
i
ranging from 0 to 15, 2
(Ci + 2)
ranges from
1
4
to
1
131072
.
The PLL core itself is driven by the 12 MHz signal from the
crystal oscillator.
The PLL can be set to lock upon the Hs signal, or to run
free at a fixed frequency or at the last frequency during
lock.
In normal operation the PLL locks to the Hs signal.
The win_PLL signal from the PSP part of the ECOBENDIC
windows the part of the picture where a VCR phase
disturbance might occur. This is normally part of the
vertical blanking period, but with the double scan
conversion and a single acquisition/display clock system,
it would become visible in the lower part of the picture as
bottom flutter. Therefore, with win_PLL active, the
frequencies generated by the PLL remain fixed at the last
frequencies during lock.
When the control bit ‘free run’ is active, a fixed frequency
will be produced, determined by the setting of PLL_div.
PLL_div = 0 gives 32 MHz, PLL_div = 1 gives 27 MHz,
PLL_div = 2 gives 24 MHz and PLL_div = 3 gives
20.25 MHz on the display clock CK2.
C
LOCK AND
R1
DIVIDER FOR MULTI PICTURE
To make simple multi picture processing, it is possible to
reduce the clock rate at the acquisition side by a
factor 2 or 3.
Suppose, a factor of 3 is chosen. Then,
1
3
of the memory
data that is normally written by 1 line of video will now be
written by 3 lines of the input video. If writing to the
memory is only enabled for a chosen
1
3
of this period, a
desired part of the video line to be displayed is updated
with a compressed line of input video. After a cycle of
3 input lines, the write pointer of the memory is located on
a position, that will be displayed exactly 1 line below. For
this essential cycle of 3 input lines, also the 16 kHz RL1
pulse must be frequency divided by 3.
U
SE OF INTERNAL AND EXTERNAL
PLL
CIRCUITS
The ECOBENDIC is designed primarily for use with its
internal (ECO)PLL circuit, providing a one clock system for
acquisition and display. It is however possible to use
external PLL circuits for either the acquisition or the display
side or both. E.g. for use in a 16 : 9 TV-set, at least one
external PLL circuit is necessary to perform horizontal
compression of any 4 : 3 program material.
To assist any external PLL function, use can be made of
the clock to line pulse dividers in the ECO-PSP and 3-state
switching on the output of such pulse, switching by the H
A
input. This may provide a VCO control voltage, if combined
with an RC filter.
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