參數(shù)資料
型號(hào)： SAA4970T
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Economical video processing IC ECOBENDIC
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO56
封裝： PLASTIC, SOT-190-1, VSOP-56
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 179K
代理商： SAA4970T
1996 Oct 25
17
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
Register 17H (RE EN’s SR)
17H
0
1
2
3
4
5
6
7
enable set 1
enable set 2
enable reset 1
enable reset 2
enables setting of rising edge 1 of RE
enables setting of rising edge 2 of RE
enables setting of falling edge 1 of RE
enables setting of falling edge 2 of RE
not used
not used
not used
not used
Registers 18H and 19H (KADer)
18H
19H
0 to 7
0 to 7
set 3 KAD
reset 3 KAD
sets third rising edge of KAD signal when register data = CNT_F
sets third falling edge of KAD signal when register data = CNT_F
Register 1AH (update Len GE)
1AH
0 to 8
update Len GE
sets rising edge of GE signal when register data = CNT_C
Register 1BH (reset CNT_F)
1BH
0 to 7
reset CNT_F
resets CNT_F when register data = CNT_F
Register 1DH (frame UV)
1DH
0
1
2
3
4
5
6
7
frame U
frame U level (0 to 15), bit 0
frame U level (0 to 15), bit 1
frame U level (0 to 15), bit 2
frame U level (0 to 15), bit 3
frame V level (0 to 15), bit 0
frame V level (0 to 15), bit 1
frame V level (0 to 15), bit 2
frame V level (0 to 15), bit 3
frame V
Register 1EH (delay)
1EH
0
1
2
3
4
5
6
7
MC2_PROC module
delay of MC2, bit 0
delay of MC2, bit 1
delay of UV against Y signal, bit 0; see Table 8
delay of UV against Y signal, bit 1; see Table 8
delay of UV against Y signal, bit 2; see Table 8
delay of Y signal against UV signals, bit 0; see Table 9
delay of Y signal against UV signals, bit 1; see Table 9
delay of Y signal against UV signals, bit 2; see Table 9
OUT_DELAY module
IN_DELAY module
REGISTER
BIT
NAME
FUNCTION
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