參數(shù)資料
型號(hào)： SAA4970T
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Economical video processing IC ECOBENDIC
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO56
封裝： PLASTIC, SOT-190-1, VSOP-56
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 179K
代理商： SAA4970T
1996 Oct 25
18
Philips Semiconductors
Preliminary specification
Economical video processing IC
(ECOBENDIC)
SAA4970T
Register 1FH (BL, H2 EN’s SR)
1FH
0
1
2
3
4
5
6
7
enable set BL
enable reset BL
enable set H2
enable reset H2
enables rising edge of BL
enables falling edge of BL
enables rising edge of H2
enables falling edge of H2
not used
not used
not used
not used
Registers 20H and 21H (PLL)
20H
0
PLL_CORE control
1 = free-run mode: not line-locked CK1/2 generation
0 = locked mode: CK1/CK2 generation is line-locked by Hs
if free-run mode (else don’t care):
1 = last frequency: generates last frequency in locked mode
0 = fixed frequency: CK1/CK2 rate is determined by PLL_div
PLL_div, bit 0; see Table 10
PLL_div, bit 1; see Table 10
0 (test bit)
MPIP processing; specifies dividing of CK1 and R1;
CK1
PLL_CORE
=
1
2
CK2; CK1 = div
×
CK1
PLL_CORE
;
R1 = div
×
16 kHz (RL1); bit 0; see Table 7
MPIP processing; specifies dividing of CK1 and R1;
CK1
PLL_CORE
=
1
2
CK2; CK1 = div
×
CK1
PLL_CORE
;
R1 = div
×
16 kHz (RL1); bit 1; see Table 7
R1 is synchronized by VI1 (= 1); no synchronisation (= 0)
coefficient n of PI filter (C
p
= 2
(n + 1)
), bit 0
coefficient n of PI filter (C
p
= 2
(n + 1)
), bit 1
coefficient n of PI filter (C
p
= 2
(n + 1)
), bit 2
coefficient m of PI filter (C
i
= 2
(m + 2)
), bit 0
coefficient m of PI filter (C
i
= 2
(m + 2)
), bit 1
coefficient m of PI filter (C
i
= 2
(m + 2)
), bit 2
coefficient m of PI filter (C
i
= 2
(m + 2)
), bit 3
1
1
2
3
4
5
DIV123 control
6
7
0
1
2
3
4
5
6
7
VI1 synchronized
n
21H
m
Register 22H (update HI pos)
22H
0 to 7
update HI pos
when register data = CNT_A then signal HI is set and CNT_B and
CNT_C are incremented
Register 23H (reset CNT_A)
23H
0 to 7
reset CNT_A
resets CNT_A when register data = CNT_A; generation of R1 output
signal, if en_R1_out = 1 and oe_CK1 = 0
Register 24H (reset GI_intAa)
24H
0 to 7
reset GI_intAa
resets Blanking-Acquisition-Interrupt
REGISTER
BIT
NAME
FUNCTION
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