參數(shù)資料
型號(hào)： SAA4977H
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Besic
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, SOT-318-2, QFP-80
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 186K
代理商： SAA4977H
1998 Jul 23
15
Philips Semiconductors
Preliminary specification
Besic
SAA4977H
7.4
Digital-to-analog conversion
Three identical 10-bit DACs are used to map the 4 : 4 : 4
data to analog levels.
7.5
Microprocessor
The SAA4977H contains an embedded 80C51
microprocessor core including a 256 byte RAM and
16 kbyte ROM. The microprocessor runs on a 16 MHz
clock, generated by dividing the 32 MHz display clock by a
factor of 2. For controlling internal registers a host
interface, consisting of a parallel address and data bus, is
built-in, that can be addressed as internal AUX RAM via
MOVX type of instructions.
7.5.1
I
2
C-
BUS
The I
2
C-bus interface in the SAA4977H is used in a slave
receive and transmit mode for communication with a
central system microprocessor. The standardized bus
frequencies of both 100 kHz and 400 kHz can be dealt
with.
The I
2
C-bus slave address of the SAA4977H is
0110100 R/W.
For a detailed description of the transmission protocol
refer to brochure “The I
2
C-bus and how to use it”(order
number 9398 393 40011) and to Application note “I
2
C-bus
register specification of the SAA4977H”(AN98054).
7.5.2
SNERT-
BUS
A SNERT interface is built-in, which operates in a master
receive and transmit mode for communication with
peripheral circuits such as the SAA4990H or
SAA4991WP. The SNERT interface replaces the standard
UART interface. In contrast to the 80C51 UART interface
there are additional special function registers and there is
no byte separation time between address and data.
The SNERT interface transforms the parallel data from the
microprocessor into 1 Mbaud SNERT data. The
SNERT-bus consists of three signals: SNCL used as the
serial clock signal and is generated by the SNERT
interface; SNDA used as the bidirectional data line, and
SNRST used as the reset signal and is generated by the
microprocessor to indicate the start of a transmission.
The read or write operation must be set by the
microprocessor. When writing to the bus, 2 bytes are
loaded by the microprocessor: one for the address, the
other for the data.
When reading from the bus, one byte is loaded by the
microprocessor for the address, the received byte is the
data from the addressed SNERT location.
7.5.3
I/O
PORTS
A parallel 8-bit I/O port (P1) is available, where P1.0 is
used as the SNERT reset signal (SNRST), P1.1 to P1.5
can be used for application specific control signals, and
P1.6 and P1.7 are used as I
2
C-bus signals (SCL and
SDA).
7.5.4
W
ATCHDOG
T
IMER
The microprocessor contains an internal Watchdog Timer,
which can be activated by setting the bit 4 in SFR PCON.
Only a synchronous reset will clear this bit. To prevent a
system reset the Watchdog Timer must be reloaded in
time. The Watchdog Timer is incremented every 0.75 ms.
The time interval between the timer’s reloading and the
occurrence of a reset depends on the reloaded 8-bit value.
7.6
Memory controller
The memory controller provides all necessary acquisition
clock related write signals (WE and RSTW) and display
clock related read signals (RE and IE2) to control one or
two-field memory concepts. Furthermore the drive signals
(HDFL and VDFL) for the horizontal and vertical deflection
power stages are generated. Also a horizontal blanking
pulse BLND is generated which can be used for peripheral
circuits as SAA4990H. The memory controller is
connected to the microprocessor via the host interface.
Start and stop values for all pulses, referring to the
corresponding horizontal or vertical reference signal, are
programmable under control of the internal software.
To allow user access to these control signals via the
I
2
C-bus a range of subaddresses is reserved; for a
detailed description of this user interface refer to
Application Note “I
2
C-bus register specification of the
SAA4977H”(AN98054).
7.6.1
WE
The write enable signal for field memory 1 is a composite
signal consisting of a horizontal and a vertical part.
The horizontal position w.r.t the rising edge of the HA
signal and the vertical position w.r.t the rising edge of the
VA signal are programmable.
相關(guān)PDF資料
PDF描述
SAA4978 Picture Improved Combined Network PICNIC
SAA4978H Picture Improved Combined Network PICNIC
SAA4979H Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4981 Monolithic integrated 16 : 9 compressor
SAA4981T Monolithic integrated 16 : 9 compressor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA4978 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC
SAA4978H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Picture Improved Combined Network PICNIC
SAA4979H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sample rate converter with embedded high quality dynamic noise reduction and expansion port
SAA4981 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor
SAA4981T 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Monolithic integrated 16 : 9 compressor
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*