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參數(shù)資料
| 型號： | SAA4977H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Besic |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, SOT-318-2, QFP-80 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大小： | 186K |
| 代理商： | SAA4977H |
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1998 Jul 23
16
Philips Semiconductors
Preliminary specification
Besic
SAA4977H
7.6.2
RSTW
Reset write signal for field memory 1; this signal is derived
from the positive edge of the VA input signal and has a
pulse width of 64
μ
s.
7.6.3
RE
The read enable signal for field memory 1 is a composite
signal consisting of a horizontal and a vertical part.
The horizontal position w.r.t the rising edge of the HA
signal and the vertical position w.r.t the rising edge of the
VA signal are programmable.
7.6.4
IE2
Input enable signal for field memory 2, can be directly set
or reset by the microprocessor.
7.6.5
HDFL
Horizontal deflection signal for driving a deflection circuit;
this signal has a cycle time of 32
μ
s and a pulse width of
76 LLD clock cycles.
7.6.6
VDFL
Vertical deflection signal for driving a deflection circuit; this
signal has a cycle time of 10 ms; the start and stop value
w.r.t the rising edge of the VA signal is programmable in
steps of 16
μ
s.
7.6.7
BLND
Horizontal blanking signal for peripheral circuits e.g.
SAA4990H, start and stop values w.r.t. the rising edge of
HRD are programmable.
7.7
Line locked clock generation
7.7.1
P
HASE COMPARISON OF
HA
RISING EDGE WITH
GENERATED
H
ref
SIGNAL
The HA signal, which has a nominal period of 64
μ
s, is
used as a timing reference for the line locked acquisition
clock system. This HA signal may vary in position from
application to application, related to the active video part.
The phase comparator measures the delay between the
HA and the internally generated, clock synchronous H
ref
signal.
7.7.2
PLL
CLOCK GENERATOR RUNNING AT
32 MH
Z
(2048
CLOCK CYCLES PER LINE
)
The basic frequency of the clock generator is 32 MHz.
The type of PLL is known as ‘Petra PLL’. This is a purely
analog clock generator, with analog frequency control via
a loop filter on the measured phase error.
7.7.3
D
IVIDE
-
BY
-2
FOR MASTER CLOCK
16 MH
Z
A simple clock divider is used to generate 16 MHz out of
32 MHz. The advantage of this construction is the inherent
50% duty cycle on the acquisition clock.
7.7.4
D
IVIDE BY ANOTHER
1024
TO GENERATE LINE
FREQUENT
,
CLOCK SYNCHRONOUS
H
ref
SIGNAL
The video lines contain 1024 clock cycles of 16 MHz.
Therefore, frequency division by 1024 creates a 50% duty
cycle line frequent signal H
ref
.
7.8
Clock and sync interfacing
Typically the circuit operates as a two clock system, i.e.
LLA is supplied with a 16 MHz clock and LLD with a
32 MHz clock.
The line locked display clock LLD must be provided by the
application. Also a line frequent signal must be provided by
the application at pin HA. A vertical 50 or 60 Hz
synchronization signal has to be applied on pin VA.
It is also possible to use an external line locked acquisition
clock, which must be provided at pin LLA. This operation
mode can be selected by the SELCLK pin. When using the
external acquisition clock the HA signal must be
synchronous to the acquisition clock.
A display clock synchronous line frequent signal is put out
at pin HRD providing a duty factor of 50%. The rising edge
of HRD is also the reference for display related control
signals as BLND, RE, HDAV and HBDA.
The acquisition clock is buffered internally and put out as
serial write clock (SWC) for supplying the field memory.
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