參數(shù)資料
型號(hào): SAA4977H
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 消費(fèi)家電
英文描述: Besic
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝: PLASTIC, SOT-318-2, QFP-80
文件頁(yè)數(shù): 23/32頁(yè)
文件大?。?/td> 186K
代理商: SAA4977H
1998 Jul 23
23
Philips Semiconductors
Preliminary specification
Besic
SAA4977H
Digital input signal: HA; timing referred to LLA clock (only when SELCLK = 0, HA used as digital horizontal
reference)
V
IH
V
IL
t
su(i)
t
h(i)
HIGH-level input voltage
LOW-level input voltage
input set-up time
input hold time
2.0
7
4
5.5
0.8
V
V
ns
ns
see Fig.10
see Fig.10
Digital input signals: TRST, TMS, RST and VA
V
IH
V
IL
HIGH-level input voltage
LOW-level input voltage
2.0
5.5
0.8
V
V
Digital input clock signal: LLA
f
LLA
δ
clk
V
IH
V
IL
t
r
t
f
sample clock frequency
clock duty factor
HIGH-level input voltage
LOW-level input voltage
clock rise time
clock fall time
14
40
2.4
16
50
34
60
0.6
5
5
MHz
%
V
V
ns
ns
see Fig.10
see Fig.10
Digital input clock signal: LLD
f
LLD
δ
clk
V
IH
V
IL
t
r
t
f
sample clock frequency
clock duty factor
HIGH-level input voltage
LOW-level input voltage
clock rise time
clock fall time
30
40
2.4
32
50
34
60
0.6
5
5
MHz
%
V
V
ns
ns
see Fig.10
see Fig.10
I
2
C-bus signal: SDA and SCL;
note 3
V
IH
V
IL
V
OL
f
SCL
t
HD;STA
t
LOW
t
HIGH
t
SU;DAT
t
SU;DAT1
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
SCL clock frequency
hold time START condition
SCL LOW time
SCL HIGH time
data set-up time
data set-up time (before
repeated START condition)
data set-up time (before STOP
condition)
set-up time repeated START
set-up time STOP condition
0.7V
DDIO
0.6
1.3
0.6
100
0.6
0.3V
DDIO
V
0.4
400
V
I
OL
= 3.0 mA
V
kHz
μ
s
μ
s
μ
s
ns
μ
s
t
SU;DAT2
0.6
μ
s
t
SU;STA
t
SU;STO
0.6
0.6
μ
s
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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