參數(shù)資料
型號： SAA7715
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 11/36頁
文件大?。?/td> 180K
代理商： SAA7715
2001 May 07
11
Philips Semiconductors
Preliminary specification
Digital Signal Processor
SAA7715H
8.5
Digital serial inputs/outputs and SPDIF inputs
8.5.1
D
IGITAL SERIAL INPUTS
/
OUTPUTS
For communication with external digital sources a digital
serial bus is implemented. It is a serial 3-line bus, having
one line for data, one line for clock and one line for the
word select. For external digital sources the SAA7715 acts
as a slave, so the external source is master and supplies
the clock.
For the I
2
S-bus format itself see the official specification
from Philips.
The digital serial input is capable of handling Philips
I
2
S-busandLSB-justifiedformatsof 16, 18, 20 and 24bits
word sizes. The sampling frequency can be 32 up to
96 kHz. See the I
2
C-bus memory map for the bits that
must be programmed, for selection of the desired serial
format.
See Fig.3 for the general waveforms of the possible
formats.
When the applied word length exceeds 24 bits, the LSBs
are skipped.
The digital serial input/output circuitry is limited in handling
the number of BCK pulses per WS period. The maximum
allowed number of bit clocks per WS period is 256. Also
the number of bit clocks during WS LOW and HIGH must
be equal (50% WS duty factor) only for the LSB-justified
formats.
There are two modes in which the digital inputs can be
used (the mode is selectable via an I
2
C-bus bit):
Use up to 4 digital serial inputs (8ch) with common WS
and BCK signal (8ch IN and 8ch OUT + 2ch FSDAC
output)
Use one of the 2 SPDIF inputs as source instead of the
use of the digital serial inputs (2ch IN and
8ch OUT + One 2ch FSDAC output).
8.5.2
SPDIF
INPUTS
Two separate SPDIF receivers are available, one shared
with digital serial input 2 (SPDIF1) and one with the digital
serial input 3 (SPDIF2). The sample frequency at which
the SPDIF inputs can be used must be in the range of
32 to 96 kHz.
There are few control signals available from the SPDIF
input stage. These are connected to flags of the DSP:
A lock signal indicating if the SPDIF input 1 or 2 is in
lock
Thepcm_audio/non-pcm_audiobitindicatingifanaudio
or data stream is detected on SPDIF input 1 or 2. The
FSDAC output will NOT be muted in the event of
non-audio PCM stream. This status bit can be read via
the I
2
C-bus, the microprocessor controller can decide to
put the DAC into MUTE (via pin POM).
Handling of channel status bits: The first 40 (of 192)
channel status bits of the selected SPDIF source (0FFBH,
bit 20), will come available in the I
2
C-bus registers
0FF2H to 0FF5H. Two registers 0FF2H to 0FF3H contain
the information for the right channel, the other two
(0FF4H to 0FF5H) contain the information for the left
channel. The information can be read via I
2
C-bus or by the
DSP program.
The design fulfils the digital audio interface specification
“IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2,
part 3, consumer applications”
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