參數(shù)資料
型號: SAA7715
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號處理器
文件頁數(shù): 4/36頁
文件大小: 180K
代理商: SAA7715
2001 May 07
4
Philips Semiconductors
Preliminary specification
Digital Signal Processor
SAA7715H
3
GENERAL DESCRIPTION
The SAA7715 is a cost effective and powerful high
performance 24-bit programmable DSP for a variety of
digital audio applications. This DSP device integrates a
24-bit DSP core with programmable memories (program
RAM/ROM, data and coefficient RAM), 4 digital serial
inputs, 4 digital serial outputs, 2 separate SPDIF
receivers, a stereo FSDAC, a standard Philips I
2
C-bus
interface, a phase-locked loop for the DSP clock
generation and a second phase-locked loop for system
clock generation (internal and external DAC clocks).
The SAA7715 can be configured for various audio
applications by downloading the dedicated DSP program
code into the DSP program RAM or using the ROM or a
combination of both. During the ‘Power-down mode’ the
contents of the memories and all other settings will keep
their values. The SAA7715 can be initialized using the
I
2
C-bus interface.
Several system application examples, based on this
existing SAA7715, are available for a wide range of audio
applications (e.g car radio DSP, DVD post-processing,
Dolby Pro Logic, PC/USB audio and more) which can be
used as a reference design for customers.
4
QUICK REFERENCE DATA
5
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
operating supply voltage
all pins V
DD
with respect to
pins V
SS
high activity of the DSP at
DSPFREQ frequency
zero input and output
signal
high activity of the DSP at
DSPFREQ frequency
pin POWERDOWN
enabled
3.15
3.3
3.45
V
I
DDD
supply current of the digital
part
supply current of the
analog part
total power dissipation
95
mA
I
DDA
20
mA
P
tot
380
mW
I
POWERDOWN
DC supply current of the
total chip in Power-down
mode
sample frequency
400
μ
A
f
s
at IIS_WS1, SPDIF1 or
SPDIF2 input
at 0 dB
at
60 dB
32
44.1
96
kHz
(THD + N)/S
DAC
total harmonic
distortion-plus-noise to
signal ratio of DAC
signal-to-noise ratio of
DAC
clock input
85
37
dB(A)
dB(A)
S/N
DAC
code = 0
100
dB(A)
CLK_IN
DIV_CLK_IN = LOW
DIV_CLK_IN = HIGH
8.192
16.384
11.2896 12.288
MHz
MHz
MHz
24.576
70
DSPFREQ
maximum DSP clock
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SAA7715H
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
SOT307-2
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