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參數(shù)資料
| 型號(hào)： | SAA8200HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Ensation Base integrated wireless audio baseband |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 15/71頁 |
| 文件大小： | 298K |
| 代理商： | SAA8200HL |
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SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
15 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
7.2 VPB0 bridge
Section 7.2
specifies the interfaces and function of the VPB0 bridge. The VPB0 bridge
acts as a bridge between a range of RTG IP blocks using the VPB bus and the EPICS7B
DIO interface. Two bridges are used one to connect to several slow blocks and an
additional one specifically for the UART.
The VPB0 bridge forms the bridge between the EPICS7B and the clock generation unit,
SRI I
2
C-bus, watchdog timer, event router, I/O configuration and the audio configuration
respectively.
7.2.1
VPB0 bridge address definitions
SRI_RX_ADDR
0x0FFC8
W
serial radio interface DMA to
MEM start address
serial radio interface DMA to
MEM block size
direct control of audio PLL M
value
direct control of audio PLL N
value
master/slave I
2
C-bus DMA
memory address
master/slave I
2
C-bus DMA
block size
master/slave I
2
C-bus control
MPI device address
0x000 0000
SRI_RX_BLKSIZE
0x0FFC7
W
0x000 0000
APLL_M
0x0FFC6
W
0x000 0000
APLL_N
0x0FFC5
W
0x000 0000
I2C_ADDR
0x0FFC4
W
0x002 8000
I2C_BLKSIZE
0x0FFC3
W
0x000 0000
I2C_CONTROL
MPI_DEVADDR
0x0FFC2
0x0FFC1
W
W
0x000 0002
0x000 0048
Table 10:
Register name
User register description
…continued
Address
R/W
Description
Reset
Table 11:
Base address Offset
0x0000
VPB0 bridge interface description
Key
Description
clock generation unit
switch control register for system PLL clock
switch control register for audio PLL clock
switch control register for DC-to-DC converter clock
switch control register for SPDIF clock
switch control register for I2SIN_1 bit clock
switch control register for I2SIN_2 bit clock
switch control register for I2SOUT bit clock
switch control register for SRI gated channel clock
switch control register for CR output 1 clock
switch control register for CR output 2 clock
switch control register for SRI reference channel clock
frequency select side 1 for system PLL clock
frequency select side 1 for audio PLL clock
frequency select side 1 for DC-to-DC converter clock
frequency select side 1 for SPDIF clock
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
SCR_LP0
SCR_HP0
SCR_DCDC
SCR_SPDIF
SCR_I2SIN_1
SCR_I2SIN_2
SCR_I2SOUT
SCR_SRI_GCHCLK
SCR_CR_CLK_OUT1
SCR_CR_CLK_OUT2
SCR_SRI_CHCLK
FS1_ LP0
FS1_ HP0
FS1_ DCDC
FS1_ SPDIF
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