
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
18 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
0x0184
0x0188
0x018C
0x0190
0x0194
0x0198
0x019C
0x01A0
0x01A4
0x01A8
0x01AC
0x01B0
0x01B4
0x01B8
0x01BC
0x01C0
0x01C4
0x01C8
0x01CC
0x01D0
0x01D4
0x01D8
0x01DC
0x01E0
0x01E4
0x01E8
0x01EC
0x01F0
0x01F4
0x01F8
0x01FC
0x0200
0x0204
0x0208
0x020C
0x0210
0x0214
0x0218
0x021C
0x0220
0x0224
PSR_WDOG_PCLK
PSR_ADC_PCLK
PSR_IOCONF_PCLK
PSR_EVENT_ROUTER_PCLK
PSR_SRI_I2C_PCLK
PSR_ADC_CLK
PSR_I2C_MS_PCLK
PSR_RSC_PCLK
PSR_EXTDMACNTR_PCLK
PSR_DIO2VPB0 _PCLK
PSR_DIO2VPB1_PCLK
PSR_I2SIN_1 _PCLK
PSR_I2SIN_2 _PCLK
PSR_I2SOUT_1 _PCLK
PSR_I2SOUT_2_PCLK
PSR_ADSS _PCLK
PSR_AUDIO_CONFIG _PCLK
PSR_SPDIF _PCLK
PSR_SRI _PCLK
PSR_FRAMESYNCREF
PSR_CR_I2SIN_2_BCK
PSR_CR_I2SIN_1_BCK
PSR_CR_I2SOUT_BCK
PSR_CR_I2SIN_2_WS
PSR_CR_I2SIN_1_WS
PSR_CR_I2SOUT_WS
PSR_SDAC_NS_CLK
PSR_SDAC_DSPCLK
PSR_SADC_DECCLK
PSR_SADC_SYSCLK
PSR_DCDC_CONVERTER_CLK power status register for DC-to-DC converter clock
PSR_SPDIF_BCK
power status register for SPDIF bit clock from pad
PSR_I2SIN_1_BCK
power status register for I2SIN_1 bit clock from pad
PSR_I2SIN_2_BCK
power status register for I2SIN_2 bit clock from pad
PSR_I2SOUT_BCK
power status register for I2SOUT bit clock from pad
PSR_SRI_GCC_SHO
power status register for SRI gated channel clock from pad
PSR_CR_CLK_OUT1
power status register for crystal output 1 from pad
PSR_CR_CLK_OUT2
power status register for crystal output 2 from pad
PSR_SRI_CHCLK
power status register for SRI channel clock
ESR_SPD_SYSCLK
enable fraction divider for system clock
ESR_SYSCLK_DIV4
enable fraction divider for 0.25
×
f
s
system clock
power status register for WDOG bus clock
power status register for control ADC bus clock
power status register for IO configuration bus clock
power status register for event router bus clock
power status register for SRI I
2
C-bus clock
power status register for control ADC system clock
power status register for M/S I
2
C-bus clock
power status register for RSC bus clock
power status register for external DMA controller clock
power status register for DIO2VPB0 bus clock
power status register for DIO2VPB1 bus clock
power status register for I2SIN_1 bus clock
power status register for I2SIN_2 bus clock
power status register for I2SOUT_1 bus clock
power status register for I2SOUT_2 bus clock
power status register for ADSS bus clock
power status register for audio configuration bus clock
power status register for SPDIF bus clock
power status register for SRI bus clock
power status register for SRI frame sync reference
power status register for I2SIN_2 bit clock
power status register for I2SIN_1 bit clock
power status register for I2SOUT bit clock
power status register for I2SIN_2 word select
power status register for I2SIN_1 word select
power status register for I2SOUT word select
power status register for SDAC new sample
power status register for SDAC DSP clock
power status register for SADC decimation filter clock
power status register for SADC system clock
Table 11:
Base address Offset
VPB0 bridge interface description
…continued
Key
Description