參數(shù)資料
型號(hào): SAA8200HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Ensation Base integrated wireless audio baseband
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù): 17/71頁(yè)
文件大小: 298K
代理商: SAA8200HL
SAA8200HL_2
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 — 17 October 2005
17 of 71
Philips Semiconductors
SAA8200HL
Ensation Base integrated wireless audio baseband
0x00E0
0x00E4
0x00E8
0x00EC
0x00F0
0x00F4
0x00F8
0x00FC
0x0100
0x0104
0x0108
0x010C
0x0110
0x0114
0x0118
0x011C
0x0120
0x0124
0x0128
0x012C
0x030
0x0134
0x0138
0x013C
0x0140
0x0144
0x0148
0x014C
0x0150
0x0154
0x0158
0x015C
0x0160
0x0164
0x0168
0x016C
0x0170
0x0174
0x0178
0x017C
0x0180
PCR_ADC_CLK
PCR_I2C_MS_PCLK
PCR_RSC_PCLK
PCR_EXTDMACNTR_PCLK
PCR_DIO2VPB0 _PCLK
PCR_DIO2VPB1_PCLK
PCR_I2SIN_1 _PCLK
PCR_I2SIN_2 _PCLK
PCR_I2SOUT_1 _PCLK
PCR_I2SOUT_2_PCLK
PCR_ADSS _PCLK
PCR_AUDIO_CONFIG _PCLK
PCR_SPDIF _PCLK
PCR_SRI _PCLK
PCR_FRAMESYNCREF
PCR_CR_I2SIN_2_BCK
PCR_CR_I2SIN_1_BCK
PCR_CR_I2SOUT_BCK
PCR_CR_I2SIN_2_WS
PCR_CR_I2SIN_1_WS
PCR_CR_I2SOUT_WS
PCR_SDAC_NS_CLK
PCR_SDAC_DSPCLK
PCR_SADC_DECCLK
PCR_SADC_SYSCLK
PCR_DCDC_CONVERTER_CLK power control register for DC-to-DC converter clock
PCR_SPDIF_BCK
power control register for SPDIF bit clock from pad
PCR_I2SIN_1_BCK
power control register for I2SIN_1 bit clock from pad
PCR_I2SIN_2_BCK
power control register for I2SIN_2 bit clock from pad
PCR_I2SOUT_BCK
power control register for I2SOUT bit clock from pad
PCR_SRI_GCC_SHO
power control register for SRI gated channel clock from pad
PCR_CR_CLK_OUT1
power control register for crystal output 1 from pad
PCR_CR_CLK_OUT2
power control register for crystal output 2 from pad
PCR_SRI_CHCLK
power control register for SRI channel clock
PSR_SPD_SYSCLK
power status register for system clock
PSR_SYSCLK_DIV4
power status register for 0.25
×
f
s
system clock
PSR_UART_UCLK
power status register for UART clock
PSR_VPB1_PCLK
power status register for VPB1 bus clock
PSR_UART_PCLK
power status register for UART bus clock
PSR_DEBOUNCE_PCLK
power status register for DEBOUNCE bus clock
PSR_CGU_PCLK
power status register for CGU bus clock
power control register for control ADC system clock
power control register for M/S I
2
C-bus clock
power control register for RSC bus clock
power control register for external DMA controller clock
power control register for DIO2VPB0 bus clock
power control register for DIO2VPB1 bus clock
power control register for I2SIN_1 bus clock
power control register for I2SIN_2 bus clock
power control register for I2SOUT_1 bus clock
power control register for I2SOUT_2 bus clock
power control register for ADSS bus clock
power control register for audio configuration bus clock
power control register for SPDIF bus clock
power control register for SRI bus clock
power control register for SRI frame sync reference
power control register for I2SIN_2 bit clock
power control register for I2SIN_1 bit clock
power control register for I2SOUT bit clock
power control register for I2SIN_2 word select
power control register for I2SIN_1 word select
power control register for I2SOUT word select
power control register for SDAC new sample
power control register for SDAC DSP clock
power control register for SADC decimation filter clock
power control register for SADC system clock
Table 11:
Base address Offset
VPB0 bridge interface description
…continued
Key
Description
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