參數(shù)資料
型號(hào)： SAH-XC2387C-136F100L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù)： 16/147頁
文件大?。?/td> 1798K
代理商： SAH-XC2387C-136F100L
XC2387C, XC2388C
XC2000 Family Derivatives / High Line
Electrical Parameters
Data Sheet
112
V1.2, 2010-09
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11
B), the system clock is
derived directly from the input clock signal CLKIN1:
f
SYS = fIN.
The frequency of
f
SYS is the same as the frequency of fIN. In this case the high and low
times of
f
SYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL1
1) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10
B, PLLCON0.VCOBY =
1
B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
f
SYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of
f
SYS equals the frequency of fOSC. In
this case the high and low times of
f
SYS are determined by the duty cycle of the input
clock
f
OSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f
SYS = fOSC / 1024.
4.7.2.1
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10
B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (
f
SYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P
× K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of
f
SYS so that it is
locked to
f
IN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage
V
DDIM.
相關(guān)PDF資料
PDF描述
SAH-XC2387C-104F100L 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
SAF-XC2387C-200F80L 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
SAF-XC2387C-200F100L 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
SAF-XC2387C-136F100L 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
SAF-XC2388C-200F100L 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
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