參數(shù)資料
型號: SAH-XC2387C-136F100L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-144
文件頁數(shù): 33/147頁
文件大小: 1798K
代理商: SAH-XC2387C-136F100L
XC2387C, XC2388C
XC2000 Family Derivatives / High Line
Electrical Parameters
Data Sheet
128
V1.2, 2010-09
Figure 24
Demultiplexed Bus Cycle
4.7.5.1
Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
Address
tpAB
tpC
tpD
tpE
tpF
t21
t11
t11/t12/t14
t20
t10
Data In
t30
t31
MC_X_EBCDEMUX
t16
t25
CLKOUT
ALE
A23-A0,
BHE, CSx
RD
WR(L/H)
D15-D0
(read)
D15-D0
(write)
Data Out
t24
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