參數(shù)資料
型號: SAK-TC1762-128F66HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 113/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F66HL
TC1762
Electrical Parameters
Preliminary
Data Sheet
94
V1.0, 2008-04
Figure 4-11
Power, Pad and Reset Timing
2) This parameter is verified by device characterization. The external oscillator circuitry must be optimized by the
customer and checked for negative resistance as recommended and specified by crystal suppliers.
3) Any HDRST activation is internally prolonged to 1024 FPI bus clock (
f
SYS) cycles.
4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST
switched-on (BYPASS = 0).
5) The setup/hold values are applicable for Port 0 and Port 4 input pins with noise suppression filter of HDRST
switched-on (BYPASS = 0), independently whether HDRST is used as input or output.
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) Not subject to production test, verified by design / characterization.
9) In case of power loss during internal flash write, prevents Flash write to random address.
10) Booting from Flash, the duration of the boot-time is defined between the rising edge of the PORST and the
moment when the first user instruction has entered the CPU and its processing starts.
11) Booting from Flash, the duration of the boot time is defined between the following events:
1. Hardware reset: the falling edge of a short HDRST pulse and the moment when the first user instruction has
entered the CPU and its processing starts, if the HDRST pulse is shorter than 1024
× T
SYS.
If the HDRST pulse is longer than 1024
× T
SYS, only the time beyond the 1024 × TSYS should be added to the
boot time (HDRST falling edge to first user instruction).
2. Software reset: the moment of starting the software reset and the moment when the first user instruction
has entered the CPU and its processing starts
reset_beh
1) as programmed
VDDP
PORST
HDRST
Pads
Pad-
state
undefined
tpi
VDD
V
DDPPA
V
DDPPA
Pad-
state
undefined
2) Tri-state, pull device active
thd
V
DDPR
OSC
toscs
1)
2)
1)
2)
tPOA
thd
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