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參數(shù)資料
| 型號： | SAK-TC1762-128F66HL |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 76/114頁 |
| 文件大?。?/td> | 852K |
| 代理商： | SAK-TC1762-128F66HL |
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TC1762
Functional Description
Preliminary
Data Sheet
60
V1.0, 2008-04
3.21
Clock Generation and PLL
The TC1762 clock system performs the following functions:
Acquires and buffers incoming clock signals to create a master clock frequency
Distributes in-phase synchronized clock signals throughout the TC1762’s entire clock
tree
Divides a system master clock frequency into lower frequencies required by the
different modules for operation.
Dynamically reduces power consumption during operation of functional units
Statically reduces power consumption through programmable power-saving modes
Reduces electromagnetic interference (EMI) by switching off unused modules
The clock system must be operational before the TC1762 can function, so it contains
special logic to handle power-up and reset operations. Its services are fundamental to
the operation of the entire system, so it contains special fail-safe logic.
Features
PLL operation for multiplying clock source by different factors
Direct drive capability for direct clocking
Comfortable state machine for secure switching between basic PLL, direct or
prescaler operation
Sleep and Power-Down Mode support
The TC1762 Clock Generation Unit (CGU) as shown in Figure 3-14 allows a very
flexible clock generation. It basically consists of an main oscillator circuit and a Phase-
Locked Loop (PLL). The PLL can converts a low-frequency external clock signal from the
oscillator circuit to a high-speed internal clock for maximum performance.
The system clock
f
SYS is generated from an oscillator clock fOSC in either one of the four
hardware/software selectable ways:
Direct Drive Mode (PLL Bypass):
In Direct Drive Mode, the TC1762 clock system is directly driven by an external clock
signal. input, i.e.
f
CPU = fOSC and fSYS = fOSC. This allows operation of the TC1762 with
a reasonably small fundamental mode crystal.
VCO Bypass Mode (Prescaler Mode):
In VCO Bypass Mode,
f
CPU and fSYS are derived from fOSC by the two divider stages,
P-Divider and K-Divider. The system clock
f
SYS is equal to fCPU.
PLL Mode:
In PLL Mode, the PLL is running. The VCO clock
f
VCO is derived from fOSC, divided by
the P factor, multiplied by the PLL (N-Divider). The clock signals
f
CPU and fSYS are
derived from
f
VCO by the K-Divider. The system clock fSYS is equal to fCPU.
PLL Base Mode:
In PLL Base Mode, the PLL is running at its VCO base frequency and
f
CPU and fSYS
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAK-TC1762-128F66HL AC | 功能描述:32位微控制器 - MCU 32 BIT SNGL-CHIP 3.3V 66MHz Flash RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| SAK-TC1762-128F80HL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:SK-TC176x Family Starter Kit |
| SAK-TC1762-128F80HL AC | 功能描述:32位微控制器 - MCU 32 BIT SNGL-CHIP 3.3V 80MHz Flash RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| SAK-TC1762-128F80HLAC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| SAK-TC1764-128F80HL | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:SK-TC176x Family Starter Kit |
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