參數(shù)資料
型號: SAK-TC1762-128F66HL
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PQFP176
封裝: PLASTIC, LQFP-176
文件頁數(shù): 77/114頁
文件大?。?/td> 852K
代理商: SAK-TC1762-128F66HL
TC1762
Functional Description
Preliminary
Data Sheet
61
V1.0, 2008-04
are derived from
f
VCO only by the K-Divider. In this mode, the system clock fSYS is
equal to
f
CPU.
Figure 3-14
Clock Generation Unit
Recommended Oscillator Circuits
The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal
oscillator or an external stable clock source. It basically consists of an inverting amplifier
and a feedback element with XTAL1 as input, and XTAL2 as output.
When using a crystal, a proper external oscillator circuitry must be connected to both
pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 4 MHz
to 25 MHz. Additionally, it is necessary to have two load capacitances
C
X1 and CX2, and
depending on the crystal type, a series resistor
R
X2, to limit the current. A test resistor RQ
may be temporarily inserted to measure the oscillation allowance (negative resistance)
of the oscillator circuitry.
R
Q values are typically specified by the crystal vendor. The CX1
and
C
X2 values shown in Figure 3-15 can be used as starting points for the negative
resistance evaluation and for non-productive systems. The exact values and related
operating range are dependent on the crystal frequency and have to be determined and
optimized together with the crystal vendor using the negative resistance method.
System Control Unit (SCU)
Clock Generation Unit (CGU)
PLL
1:1
Divider
M
U
X
M
U
X
K:1
Divider
MCA06083
Oscillator
Circuit
XTAL1
XTAL2
f
OSC
Phase
Detect.
VCO
N
Divider
f
VCO
1
0
f
SYS
Lock
Detector
OSCR
PLL_
LOCK
NDIV
[6:0]
VCO_
BYPASS
KDIV
[3:0]
PLL_
BYPASS
Register PLL_CLC
VCO_
SEL[1:0]
f
CPU
SYS
FSL
P
Divi-
der
PDIV
[2:0]
OSC
DISC
Register
OSC_CON
MOSC
OGC
BYPASS
OSC_
BYPASS
≥1
Osc. Run
Detect.
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