參數(shù)資料
型號: SC16C652BIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.) with 32-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C652BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C652BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù): 16/43頁
文件大?。?/td> 210K
代理商: SC16C652BIBS
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
16 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
TSR and UART via the THR, providing that the THR is empty. The THR empty flag in the
LSR will be set to a logic 1 when the transmitter is empty or when data is transferred to the
TSR. Note that a write operation can be performed when the THR empty flag is set
(logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C652B and
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the 16
×
clock rate. After 7
1
2
clocks, the start bit time should be
shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
Table 10:
Bit
7
Interrupt Enable Register bits description
Symbol
Description
IER[7]
CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C652B issues an interrupt when
the CTS pin transitions from a logic 0 to a logic 1.
IER[6]
RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C652B issues an interrupt when
the RTS pin transitions from a logic 0 to a logic 1.
IER[5]
Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the software flow control, receive Xoff interrupt.
IER[4]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
6
5
4
3
2
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