參數(shù)資料
型號(hào): SC16C652BIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.) with 32-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C652BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C652BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁(yè)數(shù): 18/43頁(yè)
文件大小: 210K
代理商: SC16C652BIBS
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
18 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1
DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever the FIFO (THR,
if FIFO is not enabled) is empty. Receive Ready (RXRDY) will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long
as the FIFO fill level is above the programmed trigger level.
7.3.2
FIFO mode
Table 11:
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7:6]
RCVR trigger. These bits are used to set the trigger level for the receive FIFO
interrupt.
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
Table 12
.
FCR[5:4]
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO interrupt.
The SC16C652B will issue a transmit empty interrupt when the number of
characters in FIFO drops below the selected trigger level. Refer to
Table 13
.
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C652B is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first
character is loaded into the transmit holding register.
Receive operation in mode ‘0’:
When the SC16C652B is in 16C450 mode,
or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least
one character in the receive FIFO, the RXRDY pin will be a logic 0. Once
active, the RXRDY pin will go to a logic 1 when there are no more characters
in the receiver.
5:4
3
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