參數(shù)資料
型號(hào): SC16C652BIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.) with 32-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C652BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C652BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù): 24/43頁
文件大?。?/td> 210K
代理商: SC16C652BIBS
SC16C652B_4
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 04 — 1 September 2005
24 of 43
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C652B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
[1]
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C652B provides a temporary data register to store 8 bits of user information.
Table 22:
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the loop-back mode produces the state of MCR[3] (OP2).
MSR[6]
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the loop-back mode produces the state of MCR[2] (OP1).
MSR[5]
DSR. During normal operation, this bit is the complement of the DSR input.
During the loop-back mode, this bit is equivalent to MCR[0] (DTR).
MSR[4]
CTS. During normal operation, this bit is the complement of the CTS input.
During the loop-back mode, this bit is equivalent to MCR[1] (RTS).
MSR[3]
CD
[1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
MSR[2]
RI
[1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C652B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
MSR[1]
DSR
[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
MSR[0]
CTS
[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C652B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
6
5
4
3
2
1
0
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